From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gregory CLEMENT Subject: Re: [PATCH v6 00/14] Add System Error Interrupt support to Armada SoCs Date: Tue, 02 Oct 2018 16:30:51 +0200 Message-ID: <875zyko1yc.fsf@bootlin.com> References: <20181001141358.31508-1-miquel.raynal@bootlin.com> <86a7nwvcnn.wl-marc.zyngier@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <86a7nwvcnn.wl-marc.zyngier@arm.com> (Marc Zyngier's message of "Tue, 02 Oct 2018 11:57:48 +0100") List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Marc Zyngier Cc: Mark Rutland , Andrew Lunn , Jason Cooper , devicetree@vger.kernel.org, Antoine Tenart , Catalin Marinas , Hanna Hawa , Haim Boot , Will Deacon , Maxime Chevallier , Nadav Haklai , Rob Herring , Thomas Petazzoni , Miquel Raynal , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth List-Id: devicetree@vger.kernel.org Hi Marc, On mar., oct. 02 2018, Marc Zyngier wrote: > On Mon, 01 Oct 2018 15:13:44 +0100, > Miquel Raynal wrote: >> >> The ICU is an IRQ chip found in Armada CP110. It currently has 207 wired >> inputs. Its purpose is to aggregate all CP interrupts and report them to >> the AP through MSIs. The ICU writes into GIC registers (AP side) by way >> of the interconnect. These interrupts can be of several groups: >> - SecuRe (SR); >> - Non-SecuRe (NSR); >> - System Error Interrupts (SEI); >> - RAM Error Interrupts (REI); >> - ... >> Each ICU wired interrupt can be of any of these groups. The group is >> encoded in the MSI payload. > > [...] > > I'm now ready to queue patches 1 through to 11 (with patches 6 and 9 > as of v7). Who is picking up the DT patches (12 to 14)? I will do it. Thanks, Gregory > > Thanks, > > M. > > -- > Jazz is not dead, it just smell funny. -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com