[PATCH v2 0/3] Add dma-coherent property

[PATCH v2 0/3] Add dma-coherent property

[Khairul Anuar Romli]

This patch series adds dma-coherent property for the Agilex5 platform by:

- Updating the device tree bindings for:
  - Cadence HP NAND controller (`cdns,hp-nfc`)
  - Synopsys DesignWare AXI DMA controller (`snps,dw-axi-dmac`)
  to accept the `dma-coherent` property.

- Adding the dma-coherent property to the Agilex5 device tree and wiring up
  the property to the supported peripherals:
  - NAND controller
  - DMA controller

This dma-coherent addition aligns the Agilex5 platform with ARM’s
architectural requirements for coherent interconnects.

---
Notes:
This patch series is applied and validated on socfpga dts maintainer's
branch
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

This changes is validated on:
	- intel/socfpga_agilex5_socdk.dtb
	- snps,dw-axi-dmac.yaml
	- snps,dw-axi-dmac.yaml intel/socfpga_agilex5_socdk.dtb 
	- cdns,hp-nfc.yaml 
	- cdns,hp-nfc.yaml intel/socfpga_agilex5_socdk.dtb

Changes in v2:
	- Rephrase git commit message to describe why the property is
	  needed now.
	- Remove redundant statement in the git commit message.
	- Correct the version in patch series title to v2. 
---
Khairul Anuar Romli (3):
  dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
  dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property
  arm64: dts: socfpga: agilex5: Add dma-coherent property

 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml      | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi              | 3 +++
 3 files changed, 7 insertions(+)

-- 
2.43.7

[PATCH v2 1/3] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[Khairul Anuar Romli]

The Cadence HP NAND Flash Controller on supports DMA transactions through
a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
the interconnect was non-coherent, hence there is no need for dma-coherent
property to be presence. In Agilex 5, the architecture has changed. It
introduced a coherent interconnect that supports cache-coherent DMA.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v2:
	- Rephrase commit message to describe why the property is needed now
	  and was not needed previously.
	- Remove redundant statement.
---
 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
index 73dc69cee4d8..367257a227b1 100644
--- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
@@ -40,6 +40,8 @@ properties:
   dmas:
     maxItems: 1
 
+  dma-coherent: true
+
   iommus:
     maxItems: 1
 
-- 
2.43.7

[PATCH v2 2/3] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Khairul Anuar Romli]

The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
operates on a cache-coherent AXI interface, where DMA transactions are
automatically kept coherent with the CPU caches. In previous generations
SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
is no need for dma-coherent property to be presence. In Agilex 5, the
architecture has changed. It  introduced a coherent interconnect that
supports cache-coherent DMA.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v2:
        - Rephrase commit message to describe why the property is needed now
          and was not needed previously.
        - Remove redundant statement.
---
 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index a393a33c8908..eb67348b4ab1 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -64,6 +64,8 @@ properties:
 
   dma-noncoherent: true
 
+  dma-coherent: true
+
   resets:
     minItems: 1
     maxItems: 2
-- 
2.43.7

[PATCH v2 3/3] arm64: dts: socfpga: agilex5: Add dma-coherent property

[Khairul Anuar Romli]

Add the `dma-coherent` property to these device nodes to inform the
kernel and DMA subsystem that the devices support hardware-managed
cache coherence.

Changes:
 - Add `dma-coherent` to `cdns,hp-nfc`
 - Add `dma-coherent` to both `snps,axi-dma-1.01a` instances
   (dmac0, dmac1)

This aligns the Agilex5 device tree with the coherent DMA-capable
devices accordingly.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v2:
        - No changes
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 1f5d560f97b2..d6a2fe445fa6 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -324,6 +324,7 @@ nand: nand-controller@10b80000 {
 			clock-names = "nf_clk";
 			cdns,board-delay-ps = <4830>;
 			iommus = <&smmu 4>;
+			dma-coherent;
 			status = "disabled";
 		};
 
@@ -351,6 +352,7 @@ dmac0: dma-controller@10db0000 {
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
 			iommus = <&smmu 8>;
+			dma-coherent;
 		};
 
 		dmac1: dma-controller@10dc0000 {
@@ -369,6 +371,7 @@ dmac1: dma-controller@10dc0000 {
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
 			iommus = <&smmu 9>;
+			dma-coherent;
 		};
 
 		rst: rstmgr@10d11000 {
-- 
2.43.7

Re: [PATCH v2 1/3] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[Rob Herring (Arm)]

On Wed, 03 Dec 2025 07:47:33 +0800, Khairul Anuar Romli wrote:
> The Cadence HP NAND Flash Controller on supports DMA transactions through
> a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
> the interconnect was non-coherent, hence there is no need for dma-coherent
> property to be presence. In Agilex 5, the architecture has changed. It
> introduced a coherent interconnect that supports cache-coherent DMA.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v2:
> 	- Rephrase commit message to describe why the property is needed now
> 	  and was not needed previously.
> 	- Remove redundant statement.
> ---
>  Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 2/3] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Rob Herring (Arm)]

On Wed, 03 Dec 2025 07:47:34 +0800, Khairul Anuar Romli wrote:
> The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
> operates on a cache-coherent AXI interface, where DMA transactions are
> automatically kept coherent with the CPU caches. In previous generations
> SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
> is no need for dma-coherent property to be presence. In Agilex 5, the
> architecture has changed. It  introduced a coherent interconnect that
> supports cache-coherent DMA.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v2:
>         - Rephrase commit message to describe why the property is needed now
>           and was not needed previously.
>         - Remove redundant statement.
> ---
>  Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 0/3] Add dma-coherent property

[Dinh Nguyen]

On 12/2/25 17:47, Khairul Anuar Romli wrote:
> This patch series adds dma-coherent property for the Agilex5 platform by:
> 
> - Updating the device tree bindings for:
>    - Cadence HP NAND controller (`cdns,hp-nfc`)
>    - Synopsys DesignWare AXI DMA controller (`snps,dw-axi-dmac`)
>    to accept the `dma-coherent` property.
> 
> - Adding the dma-coherent property to the Agilex5 device tree and wiring up
>    the property to the supported peripherals:
>    - NAND controller
>    - DMA controller
> 
> This dma-coherent addition aligns the Agilex5 platform with ARM’s
> architectural requirements for coherent interconnects.
> 
> ---
> Notes:
> This patch series is applied and validated on socfpga dts maintainer's
> branch
> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
> 
> This changes is validated on:
> 	- intel/socfpga_agilex5_socdk.dtb
> 	- snps,dw-axi-dmac.yaml
> 	- snps,dw-axi-dmac.yaml intel/socfpga_agilex5_socdk.dtb
> 	- cdns,hp-nfc.yaml
> 	- cdns,hp-nfc.yaml intel/socfpga_agilex5_socdk.dtb
> 
> Changes in v2:
> 	- Rephrase git commit message to describe why the property is
> 	  needed now.
> 	- Remove redundant statement in the git commit message.
> 	- Correct the version in patch series title to v2.
> ---
> Khairul Anuar Romli (3):
>    dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
>    dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property
>    arm64: dts: socfpga: agilex5: Add dma-coherent property
> 
>   Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
>   Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml      | 2 ++
>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi              | 3 +++
>   3 files changed, 7 insertions(+)
> 

Applied!

Thanks,
Dinh

Re: [PATCH v2 0/3] Add dma-coherent property

[Miquel Raynal]

>> Khairul Anuar Romli (3):
>>    dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
>>    dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property
>>    arm64: dts: socfpga: agilex5: Add dma-coherent property
>>   Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
>>   Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml      | 2 ++
>>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi              | 3 +++
>>   3 files changed, 7 insertions(+)
>> 
>
> Applied!

Have you applied all 3 patches? If yes, where? It happened during the
merge window but I see nothing in v6.19-rc1. I was about to take the mtd
binding patch, but if you took it already that's fine, I'll mark this
series as already applied.

Thanks,
Miquèl

Re: [PATCH v2 0/3] Add dma-coherent property

[Dinh Nguyen]

Hi Miquel

On 12/16/25 02:12, Miquel Raynal wrote:
> 
>>> Khairul Anuar Romli (3):
>>>     dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
>>>     dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property
>>>     arm64: dts: socfpga: agilex5: Add dma-coherent property
>>>    Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
>>>    Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml      | 2 ++
>>>    arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi              | 3 +++
>>>    3 files changed, 7 insertions(+)
>>>
>>
>> Applied!
> 
> Have you applied all 3 patches? If yes, where? It happened during the
> merge window but I see nothing in v6.19-rc1. I was about to take the mtd
> binding patch, but if you took it already that's fine, I'll mark this
> series as already applied.
> 

Yes, I took all 3 and staging it in my tree for v6.20.

Thanks,
Dinh

Re: [PATCH v2 0/3] Add dma-coherent property

[Miquel Raynal]

Hello Dinh,

>>> Applied!
>> Have you applied all 3 patches? If yes, where? It happened during the
>> merge window but I see nothing in v6.19-rc1. I was about to take the mtd
>> binding patch, but if you took it already that's fine, I'll mark this
>> series as already applied.
>> 
>
> Yes, I took all 3 and staging it in my tree for v6.20.

Noted. If you happen to rebase your own tree you can add my

Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>

on the mtd binding patch. Otherwise, well, too late.

Thanks!
Miquèl

Re: [PATCH v2 0/3] Add dma-coherent property

[Dinh Nguyen]

On 12/17/25 03:05, Miquel Raynal wrote:
> Hello Dinh,
> 
>>>> Applied!
>>> Have you applied all 3 patches? If yes, where? It happened during the
>>> merge window but I see nothing in v6.19-rc1. I was about to take the mtd
>>> binding patch, but if you took it already that's fine, I'll mark this
>>> series as already applied.
>>>
>>
>> Yes, I took all 3 and staging it in my tree for v6.20.
> 
> Noted. If you happen to rebase your own tree you can add my
> 
> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
> 

I'll do that.

Thanks,
Dinh