From: Andreas Schwab <schwab@linux-m68k.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN
Date: Thu, 10 Feb 2022 22:58:09 +0100 [thread overview]
Message-ID: <877da2xu32.fsf@igel.home> (raw)
In-Reply-To: <20220210214018.55739-6-atishp@rivosinc.com> (Atish Patra's message of "Thu, 10 Feb 2022 13:40:17 -0800")
On Feb 10 2022, Atish Patra wrote:
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 469b9739faf7..cca579bae8a0 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
> for_each_of_cpu_node(node) {
> unsigned long this_hwcap = 0;
> uint64_t this_isa = 0;
> + char *temp;
>
> if (riscv_of_processor_hartid(node) < 0)
> continue;
> @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
> continue;
> }
>
> + temp = (char *)isa;
There should be no need for this cast.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
next prev parent reply other threads:[~2022-02-10 22:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-10 21:40 [PATCH v2 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-02-10 21:40 ` [PATCH v2 1/6] RISC-V: Correctly print supported extensions Atish Patra
2022-02-10 21:40 ` [PATCH v2 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-02-10 21:40 ` [PATCH v2 3/6] RISC-V: Extract multi-letter extension names from "riscv,isa" Atish Patra
2022-02-10 21:40 ` [PATCH v2 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
2022-02-14 20:05 ` Heiko Stübner
2022-02-14 20:14 ` Atish Patra
2022-02-14 20:24 ` Heiko Stübner
2022-02-14 20:42 ` Atish Patra
2022-02-14 22:22 ` Heiko Stübner
2022-02-14 23:22 ` Atish Kumar Patra
2022-02-15 9:12 ` Atish Kumar Patra
2022-02-15 9:48 ` Heiko Stübner
2022-02-15 9:50 ` Heiko Stübner
2022-02-16 0:47 ` Atish Kumar Patra
2022-02-10 21:40 ` [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra
2022-02-10 21:58 ` Andreas Schwab [this message]
2022-02-11 12:52 ` Geert Uytterhoeven
2022-02-14 20:15 ` Atish Patra
2022-02-14 20:06 ` Heiko Stübner
2022-02-10 21:40 ` [PATCH v2 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-02-14 20:07 ` Heiko Stübner
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