From: Thomas Gleixner <tglx@linutronix.de>
To: Claudiu <claudiu.beznea@tuxon.dev>,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, geert+renesas@glider.be,
magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org,
prabhakar.mahadev-lad.rj@bp.renesas.com
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 4/7] irqchip/renesas-rzg2l: implement restriction when writing ISCR register
Date: Fri, 27 Oct 2023 20:02:30 +0200 [thread overview]
Message-ID: <878r7o2bbd.ffs@tglx> (raw)
In-Reply-To: <20231023102223.1309614-5-claudiu.beznea.uj@bp.renesas.com>
On Mon, Oct 23 2023 at 13:22, Claudiu wrote:
> In hardware manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf)
This filename is completely useless.
> is available the following statement with regards to clearing
> interrupts
The RZ/G2L manual describes the operation to clear interrupts
> though ISCR register:
through the ISCR ...
>
> [Write operation]
> When "Falling-edge detection", "Rising-edge detection" or
> "Falling/Rising-edge detection" is set in ISCR.:
> - In case ISTAT is 1
> 0: IRQn interrupt detection status is cleared.
> 1: Invalid to write.
> - In case ISTAT is 0
> Invalid to write.
> When “Low-level detection” is set in IITSR.:
> Invalid to write.
>
> Thus, take into account interrupt type when clearing interrupts though
take the interrupt type into account... through the ISCR ...
> ISCR register.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
> index 9ce0d6d67486..1ed9cb7178fa 100644
> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -73,11 +73,17 @@ static void rzg2l_irq_eoi(struct irq_data *d)
> unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
> struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> u32 bit = BIT(hw_irq);
> - u32 reg;
> + u32 iitsr, iscr;
>
> - reg = readl_relaxed(priv->base + ISCR);
> - if (reg & bit)
> - writel_relaxed(reg & ~bit, priv->base + ISCR);
> + iscr = readl_relaxed(priv->base + ISCR);
> + iitsr = readl_relaxed(priv->base + IITSR);
> +
> + /*
> + * ISCR could be cleared only if type is falling-edge, rising-edge or
ISCR can only be cleared if the type is ...
> + * falling/rising-edge.
> + */
> + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq)))
> + writel_relaxed(iscr & ~bit, priv->base + ISCR);
> }
>
> static void rzg2l_tint_eoi(struct irq_data *d)
next prev parent reply other threads:[~2023-10-27 18:02 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 10:22 [PATCH 0/7] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
2023-10-23 10:22 ` [PATCH 1/7] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: document RZ/G3S Claudiu
2023-10-23 16:19 ` Conor Dooley
2023-10-23 10:22 ` [PATCH 2/7] clk: renesas: r9a08g045: add IA55 pclk and its reset Claudiu
2023-10-23 10:22 ` [PATCH 3/7] irqchip/renesas-rzg2l: add macros to retrieve TITSR index and associated selector Claudiu
2023-10-27 17:58 ` Thomas Gleixner
2023-10-23 10:22 ` [PATCH 4/7] irqchip/renesas-rzg2l: implement restriction when writing ISCR register Claudiu
2023-10-27 18:02 ` Thomas Gleixner [this message]
2023-10-23 10:22 ` [PATCH 5/7] irqchip/renesas-rzg2l: cache registers on suspend/resume Claudiu
2023-10-27 17:57 ` Thomas Gleixner
2023-10-23 10:22 ` [PATCH 6/7] irqchip/renesas-rzg2l: use tabs instead of spaces Claudiu
2023-10-27 17:57 ` Thomas Gleixner
2023-10-23 10:22 ` [PATCH 7/7] arm64: dts: renesas: r9108g045: add irqc Claudiu
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