From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 691ABC433EF for ; Wed, 8 Dec 2021 16:02:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236460AbhLHQFy (ORCPT ); Wed, 8 Dec 2021 11:05:54 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:40008 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236426AbhLHQFy (ORCPT ); Wed, 8 Dec 2021 11:05:54 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id A67FECE2207; Wed, 8 Dec 2021 16:02:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAEA9C00446; Wed, 8 Dec 2021 16:02:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638979338; bh=aYzMTGF66BBpR2FANCUsedAiT55w3D5TjpGIfAfKn1Q=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ULuDyyrIlxD/4XyzOSQyQM7tCBY/fMl3HwzHkXWZW4WoPCwXCdr+JomLb3OsNorTA PN8OIRJkJTpOPeXycNVMq3LB8hDUJkZVvJ+rQjFqxbV852WEQGxIDaakhBH0cBd4HY yTtwhAOlcIqP3oj1OduxhAbLKV/l/P67A5PYL6lZLR0eDVxN0RU3qb+q0H2YJmjRK3 dzsO7ln3IN9c87hCXD6briXJfpujzj8NutqyliZphyRDAhIUqa8t6z7JbG7EwZBpAa MUadmBF9t4LR80ws8rW+Feg+XI3t4u/+L6K4c36UldbGnAqUjX0A6Zgb5GFvmjuAjX nnB5vHnWCA7cg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1muzOa-00AoNQ-Q0; Wed, 08 Dec 2021 16:02:16 +0000 Date: Wed, 08 Dec 2021 16:02:16 +0000 Message-ID: <87a6hb13w7.wl-maz@kernel.org> From: Marc Zyngier To: =?UTF-8?B?InFpbmppYW5b6KaD5YGlXSI=?= Cc: "robh+dt@kernel.org" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "tglx@linutronix.de" , "p.zabel@pengutronix.de" , "linux@armlinux.org.uk" , "broonie@kernel.org" , "arnd@arndb.de" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , Wells Lu =?UTF-8?B?5ZGC6Iqz6aiw?= Subject: Re: [PATCH v5 08/10] irqchip: Add Sunplus SP7021 interrupt controller driver In-Reply-To: <8fa00c3b55874e90b5baae1f84010997@cqplus1.com> References: <87r1ao23fp.wl-maz@kernel.org> <39f9b853af7c44cb94421354744512a8@cqplus1.com> <8fa00c3b55874e90b5baae1f84010997@cqplus1.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: qinjian@cqplus1.com, robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, p.zabel@pengutronix.de, linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, 08 Dec 2021 09:28:42 +0000, "qinjian[=E8=A6=83=E5=81=A5]" wrote: >=20 > > -----Original Message----- > > From: Marc Zyngier > > Sent: Wednesday, December 8, 2021 3:45 PM > > To: qinjian[=E8=A6=83=E5=81=A5] > > Cc: robh+dt@kernel.org; mturquette@baylibre.com; sboyd@kernel.org; tglx= @linutronix.de; p.zabel@pengutronix.de; > > linux@armlinux.org.uk; broonie@kernel.org; arnd@arndb.de; linux-arm-ker= nel@lists.infradead.org; devicetree@vger.kernel.org; linux- > > kernel@vger.kernel.org; linux-clk@vger.kernel.org; Wells Lu =E5=91=82= =E8=8A=B3=E9=A8=B0 > > Subject: Re: [PATCH v5 08/10] irqchip: Add Sunplus SP7021 interrupt con= troller driver > >=20 > > On 2021-12-08 07:15, qinjian[=E8=A6=83=E5=81=A5] wrote: > > >> > +void sp_intc_set_ext(u32 hwirq, int ext_num) > > >> > +{ > > >> > + sp_intc_assign_bit(hwirq, REG_INTR_PRIORITY, !ext_num); > > >> > +} > > >> > +EXPORT_SYMBOL_GPL(sp_intc_set_ext); > > >> > > >> No way. We don't export random symbols without a good justification, > > >> and you didn't give any. > > >> > > > > > > This function called by SP7021 display driver to decide DISPLAY_IRQ > > > routing to which parent irq (EXT_INT0 or EXT_INT1). > >=20 > > Based on what? How can a display driver decide which parent is > > appropriate? What improvement does this bring? >=20 > In default, all IRQ routing to EXT_INT0, which processed by CPU0 > Some device's IRQ need low latency, like display, so routing > DISPLAY_IRQ to EXT_INT1, which processed by CPU1 (set > /proc/irq//smp_affinity_list) Why would that have a lower latency? What if CPU1 is busy with interrupts disabled most of the time? How does the display driver finds out what is better? And if you really wanted a lower latency, why route the interrupt via a secondary interrupt controller, instead of attaching it directly to the upstream GIC? I really don't think this is an acceptable thing to do. Configure the interrupt route statically if you want, but we're not exposing this sort of SoC-specific API to other drivers. M. --=20 Without deviation from the norm, progress is not possible.