From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5399AC433EF for ; Tue, 3 May 2022 15:56:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239025AbiECQA0 (ORCPT ); Tue, 3 May 2022 12:00:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233041AbiECQAZ (ORCPT ); Tue, 3 May 2022 12:00:25 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE45421E3A; Tue, 3 May 2022 08:56:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 79589B81EB8; Tue, 3 May 2022 15:56:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3029CC385A4; Tue, 3 May 2022 15:56:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651593410; bh=yLgv+wqjkaIZgbsKQ6TfodDHyXt26mq0elWPo6njigU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=dhgSF+zjy5Ffe5isKT2GTwYJS7C5JXBW7EmkeDwDcQJu94mQBg0A2QVhw/ltHzJnK CfBc90HR0sW71FhhfPMf3wVqAOa2H5hDdwCiASqaFTaOHiq3d6FR9bTs+TpH0Pt+EV ldpoa3/CiAjsgQj8DT4IavwWMx2xedrO9h5fh5885C23D1yCGcT/XJhDa8bbhkeeLT +7qUTq853OWvh7wEe8nNDmsEBSsR44GLRebUsArj4PNXQuUp4Py8ceaX/CU0ELygqe SCPKD5ffk+zAvHcyqHHQV/SAbZRB0CpfyGokom51VfS1fL3qmVm3KVqUTXSJnc2CdY kgdRmDhVs9w+A== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nlutL-008gpO-J5; Tue, 03 May 2022 16:56:47 +0100 Date: Tue, 03 May 2022 16:56:47 +0100 Message-ID: <87bkwe8v9c.wl-maz@kernel.org> From: Marc Zyngier To: Geert Uytterhoeven Cc: Phil Edworthy , Rob Herring , Krzysztof Kozlowski , Biju Das , Daniel Lezcano , Thomas Gleixner , Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux-Renesas Subject: Re: [PATCH v3 04/12] dt-bindings: timer: arm,arch_timer: Add optional clock and reset In-Reply-To: References: <20220503115557.53370-1-phil.edworthy@renesas.com> <20220503115557.53370-5-phil.edworthy@renesas.com> <6fb57bcc87e091d6e88217d2b82af9da@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: geert@linux-m68k.org, phil.edworthy@renesas.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, biju.das.jz@bp.renesas.com, daniel.lezcano@linaro.org, tglx@linutronix.de, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Geert, On Tue, 03 May 2022 15:22:35 +0100, Geert Uytterhoeven wrote: > > Hi Marc, > > On Tue, May 3, 2022 at 3:12 PM Marc Zyngier wrote: > > On 2022-05-03 12:55, Phil Edworthy wrote: > > > Some SoCs use a gated clock for the timer and the means to reset the > > > timer. > > > Hence add these as optional. > > > > The architecture is crystal clear on the subject: the counter > > is in an always-on domain. Why should this be visible to SW? > > Also, reseting the counter breaks the guaranteed monotonicity > > we rely on. > > The DT bindings do state: > > always-on: > type: boolean > description: If present, the timer is powered through an always-on power > domain, therefore it never loses context. > > and (surprisingly?) the absence of this property seems to be the > norm... *timer* is the key word. And counter != timer. What your HW has is a gate on the *counter* which is illegal if observable from NS SW. > > And: > > arm,no-tick-in-suspend: > type: boolean > description: The main counter does not tick when the system is in > low-power system suspend on some SoCs. This behavior does not match the > Architecture Reference Manual's specification that the system > counter "must > be implemented in an always-on power domain." > > So there's already precedent for clocks that can be disabled. No, this is only the case in *suspend*, as the name of the property vaguely hints at. And that's a property for a bug. In your case, the clock can be controlled arbitrarily, which is even worse. > > > Worse case, this belongs to the boot firmware, not the kernel, > > and I don't think this should be described in the DT. > > "DT describes hardware, not software policy"? I'm happy to spread "always-on" properties all over the shop, but that's not helping. The HW spec says it in bold letters: the counter is always running, and doesn't jump backward. I can't imagine how secure SW will behave when you reset its counter... :-/ M. -- Without deviation from the norm, progress is not possible.