From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C394BC433F5 for ; Fri, 11 Feb 2022 11:33:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349471AbiBKLdT (ORCPT ); Fri, 11 Feb 2022 06:33:19 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:48996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234009AbiBKLdS (ORCPT ); Fri, 11 Feb 2022 06:33:18 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 035B9B3B; Fri, 11 Feb 2022 03:33:18 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9172D61880; Fri, 11 Feb 2022 11:33:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F027AC340E9; Fri, 11 Feb 2022 11:33:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1644579197; bh=msKcb0RndZ12+vVaLK7an78KdGVqce9K77/Gi6nEqrw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=sVEMcA5CAW3nFHt5iIl85Vamh8nGFsN3fzHTiuSQzJ2NbpQEwMgZnfo/+dhEoasL9 8WTwRkXnF9cUkVGXOHTWV3xzq5M9d8v/FD7XJVTWkqwKUYwMWmXoxEvdOMqgOVbhSp /4K80Aam5kTJTMws2GxKWhmfMy3evXdpMFh5N+Laqnc5hUksjKyNUw5LZc0qx8fXG7 TfgCx0WZBMHLudBuTC2gCjoPFGpBBhk6IVz+fqrJJPWr04YINhLACkN2CEX9RlP8b2 A85bZe9BNvn+ArwYEh3fOFJ0cjIkKErYpRJkUge+oA9fqRHDs0sHC84M9VIN8d59KQ CB/j8dOr+ICJg== Received: from sofa.misterjones.org ([185.219.108.64] helo=billy-the-mountain.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nIUAs-0079XQ-VF; Fri, 11 Feb 2022 11:33:15 +0000 Date: Fri, 11 Feb 2022 11:33:14 +0000 Message-ID: <87bkzdljt1.wl-maz@kernel.org> From: Marc Zyngier To: Nishanth Menon Cc: Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Santosh Shilimkar , , , Subject: Re: [PATCH 4/5] arm64: dts: ti: Introduce base support for AM62x SoC In-Reply-To: <20220210193459.nl6baranvmqs46bi@coastal> References: <20220208131827.1430086-1-vigneshr@ti.com> <20220208131827.1430086-5-vigneshr@ti.com> <20220210193459.nl6baranvmqs46bi@coastal> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski@canonical.com, ssantosh@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 10 Feb 2022 19:34:59 +0000, Nishanth Menon wrote: > > On 19:10-20220209, Marc Zyngier wrote: > [...] > > > > +&cbass_main { > > > + gic500: interrupt-controller@1800000 { > > > + compatible = "arm,gic-v3"; > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + ranges; > > > + #interrupt-cells = <3>; > > > + interrupt-controller; > > > + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ > > > + <0x00 0x01880000 0x00 0xC0000>; /* GICR */ > > > > Usual rant: you are missing the GICC, GICH and GICV regions > > that are implemented by the CPU. Cortex-A53 implements them > > (they are not optional), so please describe them. > > > > > -ECONFUSED. TRM for GIC500 refers to just GICD, GICR and ITS range[1]. And I'm not talking about the GIC, but of the CPU interface. The fact that we describe both in the GIC binding doesn't mean they are implemented by the same IP block (and the architecture is quite clear about that). > Same thing is indicated by Generic Interrupt Controller Architecture > Specification[2] See table 1-1 (page 23). > > I think you are expecting GICV3's backward compatibility mode (Table 1-2 > in page 24), But in K3 architecture, are_option meant for backward > compatibility is set to true (aka no backward compatibility). I think > this did popup sometime back as well (first k3 SoC)[3]. I think the more > clearer description is available in [4]. No, this description is for the architecture as a whole. ARE being disabled *int the GIC* doesn't mean it is disabled overall, and the CPU is free to implement the CPU interface by any mean it wants as long as it communicates with the GIC using the Stream Protocol. Cortex-A32, A34, 35, A53, A57, A72 and A73 all implement both the sysreg and MMIO CPU interfaces. Later ARM CPUs don't. Both can work with GIC500. > I believe the argumentation that GICC/H/V is mandatory for A53 if GIC500 > is used is not accurate. Please correct me if I am mistaken. GIC500 is not involved at all, and A53 always implements both the system register and MMIO interfaces. See the A53 TRM, chapter 9. The only way to disable this interface is to assert GICCDISABLE, which disables the whole of the CPU interface. Given that you have a (more or less) functional system, it probably isn't the case. See Table 9-1, which tells you where these registers are as an offset from PERIPHBASE. Dumping these registers should show you that they are indeed implemented and not solely a figment of my own imagination. Thanks, M. -- Without deviation from the norm, progress is not possible.