From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: "Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Saravana Kannan" <saravanak@google.com>,
"Anup Patel" <anup@brainfault.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
"Anup Patel" <apatel@ventanamicro.com>
Subject: Re: [PATCH v13 03/13] irqchip/riscv-intc: Add support for RISC-V AIA
Date: Tue, 20 Feb 2024 11:13:14 +0100 [thread overview]
Message-ID: <87cysrigud.ffs@tglx> (raw)
In-Reply-To: <20240220060718.823229-4-apatel@ventanamicro.com>
On Tue, Feb 20 2024 at 11:37, Anup Patel wrote:
> The RISC-V advanced interrupt architecture (AIA) extends the per-HART
> local interrupts in following ways:
> 1. Minimum 64 local interrupts for both RV32 and RV64
> 2. Ability to process multiple pending local interrupts in same
> interrupt handler
> 3. Priority configuration for each local interrupts
> 4. Special CSRs to configure/access the per-HART MSI controller
>
> We add support for #1 and #2 described above in the RISC-V intc
> driver.
S/We add/Add/
> +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs)
> +{
> + unsigned long topi;
> +
> + while ((topi = csr_read(CSR_TOPI)))
> + generic_handle_domain_irq(intc_domain,
> + topi >> TOPI_IID_SHIFT);
Please let it stick out. You got 100 characters. All over the place.
Thanks,
tglx
next prev parent reply other threads:[~2024-02-20 10:13 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-20 6:07 [PATCH v13 00/13] Linux RISC-V AIA Support Anup Patel
2024-02-20 6:07 ` [PATCH v13 01/13] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-02-20 10:09 ` Thomas Gleixner
2024-02-22 9:25 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 02/13] irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore Anup Patel
2024-02-20 10:11 ` Thomas Gleixner
2024-02-21 13:35 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 03/13] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2024-02-20 10:13 ` Thomas Gleixner [this message]
2024-02-21 13:32 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 04/13] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-02-20 6:07 ` [PATCH v13 05/13] genirq/matrix: Dynamic bitmap allocation Anup Patel
2024-02-20 6:07 ` [PATCH v13 06/13] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-02-20 11:52 ` Björn Töpel
2024-02-20 13:00 ` Anup Patel
2024-02-21 11:59 ` Björn Töpel
2024-02-21 12:23 ` Anup Patel
2024-02-21 17:22 ` Björn Töpel
2024-02-20 11:53 ` Björn Töpel
2024-02-20 13:15 ` Anup Patel
2024-02-20 13:15 ` Thomas Gleixner
2024-02-20 16:33 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-02-20 11:53 ` Björn Töpel
2024-02-20 16:39 ` Anup Patel
2024-02-20 13:32 ` Thomas Gleixner
2024-02-20 16:52 ` Anup Patel
2024-02-20 17:12 ` Thomas Gleixner
2024-02-20 6:07 ` [PATCH v13 08/13] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-02-20 13:35 ` Thomas Gleixner
2024-02-20 17:21 ` Anup Patel
2024-02-20 20:03 ` Thomas Gleixner
2024-02-20 6:07 ` [PATCH v13 09/13] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-02-20 6:07 ` [PATCH v13 10/13] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2024-02-20 13:40 ` Thomas Gleixner
2024-02-21 5:42 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 11/13] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-02-20 6:07 ` [PATCH v13 12/13] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-02-20 6:07 ` [PATCH v13 13/13] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2024-02-20 11:52 ` [PATCH v13 00/13] Linux RISC-V AIA Support Björn Töpel
2024-02-20 13:09 ` Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87cysrigud.ffs@tglx \
--to=tglx@linutronix.de \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=apatel@ventanamicro.com \
--cc=atishp@atishpatra.org \
--cc=bjorn@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=saravanak@google.com \
--cc=sunilvl@ventanamicro.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).