From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C75EBC433FE for ; Mon, 4 Oct 2021 09:05:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB6DC613A8 for ; Mon, 4 Oct 2021 09:05:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231303AbhJDJHg (ORCPT ); Mon, 4 Oct 2021 05:07:36 -0400 Received: from mail.kernel.org ([198.145.29.99]:52710 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230022AbhJDJHf (ORCPT ); Mon, 4 Oct 2021 05:07:35 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0EC18613A2; Mon, 4 Oct 2021 09:05:47 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mXJur-00EZok-3A; Mon, 04 Oct 2021 10:05:45 +0100 Date: Mon, 04 Oct 2021 10:05:44 +0100 Message-ID: <87czolrwgn.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bjorn Helgaas , Rob Herring , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Alyssa Rosenzweig , Stan Skowronek , Mark Kettenis , Sven Peter , Hector Martin , Robin Murphy , Joey Gouly , Joerg Roedel , kernel-team@android.com, Linus Walleij , Arnd Bergmann Subject: Re: [PATCH v5 00/14] PCI: Add support for Apple M1 In-Reply-To: <20211004083845.GA22336@lpieralisi> References: <20210929163847.2807812-1-maz@kernel.org> <20211004083845.GA22336@lpieralisi> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lorenzo.pieralisi@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, kw@linux.com, alyssa@rosenzweig.io, stan@corellium.com, kettenis@openbsd.org, sven@svenpeter.dev, marcan@marcan.st, Robin.Murphy@arm.com, joey.gouly@arm.com, joro@8bytes.org, kernel-team@android.com, linus.walleij@linaro.org, arnd@arndb.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Lorenzo, [+LinusW, Arnd] On Mon, 04 Oct 2021 09:38:45 +0100, Lorenzo Pieralisi wrote: > > On Wed, Sep 29, 2021 at 05:38:33PM +0100, Marc Zyngier wrote: > > This is v5 of the series adding PCIe support for the M1 SoC. Not a lot > > has changed this time around, and most of what I was saying in [1] is > > still valid. > > > > Very little has changed code wise (a couple of bug fixes). The series > > however now carries a bunch of DT updates so that people can actually > > make use of PCIe on an M1 box (OK, not quite, you will still need [2], > > or whatever version replaces it). The corresponding bindings are > > either already merged, or queued for 5.16 (this is the case for the > > PCI binding). > > > > It all should be in a state that makes it mergeable (yeah, I said that > > last time... I mean it this time! ;-). > > > > As always, comments welcome. > > > > M. > > > > [1] https://lore.kernel.org/r/20210922205458.358517-1-maz@kernel.org > > [2] https://lore.kernel.org/r/20210921222956.40719-2-joey.gouly@arm.com > > > > Alyssa Rosenzweig (2): > > PCI: apple: Add initial hardware bring-up > > PCI: apple: Set up reference clocks when probing > > > > Marc Zyngier (10): > > irqdomain: Make of_phandle_args_to_fwspec generally available > > of/irq: Allow matching of an interrupt-map local to an interrupt > > controller > > PCI: of: Allow matching of an interrupt-map local to a PCI device > > PCI: apple: Add INTx and per-port interrupt support > > PCI: apple: Implement MSI support > > iommu/dart: Exclude MSI doorbell from PCIe device IOVA range > > PCI: apple: Configure RID to SID mapper on device addition > > arm64: dts: apple: t8103: Add PCIe DARTs > > arm64: dts: apple: t8103: Add root port interrupt routing > > arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address > > > > Mark Kettenis (2): > > arm64: apple: Add pinctrl nodes > > arm64: apple: Add PCIe node > > > > MAINTAINERS | 7 + > > arch/arm64/boot/dts/apple/t8103-j274.dts | 23 + > > arch/arm64/boot/dts/apple/t8103.dtsi | 203 ++++++ > > drivers/iommu/apple-dart.c | 27 + > > drivers/of/irq.c | 17 +- > > drivers/pci/controller/Kconfig | 17 + > > drivers/pci/controller/Makefile | 1 + > > drivers/pci/controller/pcie-apple.c | 822 +++++++++++++++++++++++ > > drivers/pci/of.c | 10 +- > > include/linux/irqdomain.h | 4 + > > kernel/irq/irqdomain.c | 6 +- > > 11 files changed, 1127 insertions(+), 10 deletions(-) > > create mode 100644 drivers/pci/controller/pcie-apple.c > > I have applied (with very minor log changes) patches [1-9] to > pci/apple for v5.16, I expect the dts changes to go via the > arm-soc tree separately, please let me know if that works for you. Yes, that's absolutely fine. I hope we can resolve the issue on the pinctrl binding pretty quickly, and get the arm-soc folks to pull the DT changes in for 5.16 too. This would make the Mini a usable machine with a mainline kernel. Thanks, M. -- Without deviation from the norm, progress is not possible.