From: Thomas Gleixner <tglx@linutronix.de>
To: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Sunil V L <sunilvl@ventanamicro.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Ryo Takakura <takakura@valinux.co.jp>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, sophgo@lists.linux.dev,
Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Subject: Re: [PATCH v2 4/7] irqchip: MIPS P800 variant of aclint-sswi
Date: Thu, 12 Jun 2025 15:03:54 +0200 [thread overview]
Message-ID: <87ecvpru11.ffs@tglx> (raw)
In-Reply-To: <20250610100540.2834044-5-vladimir.kondratiev@mobileye.com>
On Tue, Jun 10 2025 at 13:05, Vladimir Kondratiev wrote:
> +config ACLINT_SSWI
> + bool
> +
> +config MIPS_P8700_ACLINT_SSWI
> + bool "MIPS P8700 ACLINT S-mode IPI Interrupt Controller"
> + depends on RISCV
> + depends on SMP
> + select IRQ_DOMAIN_HIERARCHY
> + select GENERIC_IRQ_IPI_MUX
> + select ACLINT_SSWI
> + help
> + This enables support for MIPS P8700 specific ACLINT SSWI device
> +
> + If you don't know what to do here, say Y.
> +
> config THEAD_C900_ACLINT_SSWI
> bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller"
> depends on RISCV
> depends on SMP
> select IRQ_DOMAIN_HIERARCHY
> select GENERIC_IRQ_IPI_MUX
> + select ACLINT_SSWI
> help
> This enables support for T-HEAD specific ACLINT SSWI device
> support.
That's just exactly the same thing twice for no value. Just rename it to
ACLINT_SSWI and have a list of supported chips in the help text.
The only issue with the rename is, that oldconfig will drop the then
non-existing THEAD_C900_ACLINT_SSWI entry in the previous config. That's
not the end of the world and if really desired this can be solved by
having:
config ACLINT_SSWI
bool "RISCV ACLINT ...."
depends on RISCV
depends on SMP
select IRQ_DOMAIN_HIERARCHY
select GENERIC_IRQ_IPI_MUX
select ACLINT_SSWI
help
This enables support for ACLINT SSWI device on THEAD C9XX and
MIPS P8700 devices.
# Backwards compatibility so oldconfig does not drop it.
config THEAD_C900_ACLINT_SSWI
select ACLINT_SSWI
Or something like that.
Thanks,
tglx
next prev parent reply other threads:[~2025-06-12 13:03 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-09 13:47 [PATCH v1 0/7] Risc-V ACLINT IPI controller Vladimir Kondratiev
2025-06-09 13:47 ` [PATCH v1 1/7] riscv: helper to parse hart index Vladimir Kondratiev
2025-06-23 12:53 ` Alexandre Ghiti
2025-06-09 13:47 ` [PATCH v1 2/7] irqchip: riscv aplic: use riscv_get_hart_index() Vladimir Kondratiev
2025-06-12 12:50 ` Thomas Gleixner
2025-06-09 13:47 ` [PATCH v1 3/7] dt-bindings: interrupt-controller: add generic Risc-v aclint-sswi Vladimir Kondratiev
2025-06-09 16:01 ` Conor Dooley
2025-06-10 9:55 ` Vladimir Kondratiev
2025-06-09 13:47 ` [PATCH v1 4/7] irqchip: introduce generic Risc-V aclint-sswi Vladimir Kondratiev
2025-06-09 13:47 ` [PATCH v1 5/7] irqchip: aslint-sswi: resolve hart index Vladimir Kondratiev
2025-06-09 13:47 ` [PATCH v1 6/7] irqchip: aclint-sswi: reduce data scope Vladimir Kondratiev
2025-06-09 13:47 ` [PATCH v1 7/7] irqchip: aclint-sswi: remove extra includes Vladimir Kondratiev
2025-06-10 10:05 ` [PATCH v2 0/7] MIPS P8700 variant of the ACLINT IPI controller Vladimir Kondratiev
2025-06-10 10:05 ` [PATCH v2 1/7] riscv: helper to parse hart index Vladimir Kondratiev
2025-06-10 10:05 ` [PATCH v2 2/7] irqchip: riscv aplic: use riscv_get_hart_index() Vladimir Kondratiev
2025-06-10 10:05 ` [PATCH v2 3/7] dt-bindings: interrupt-controller: add MIPS P8700 aclint-sswi Vladimir Kondratiev
2025-06-10 10:05 ` [PATCH v2 4/7] irqchip: MIPS P800 variant of aclint-sswi Vladimir Kondratiev
2025-06-10 10:09 ` Inochi Amaoto
2025-06-10 10:46 ` Vladimir Kondratiev
2025-06-10 10:53 ` Inochi Amaoto
2025-06-10 11:09 ` Vladimir Kondratiev
2025-06-10 11:20 ` Inochi Amaoto
2025-06-12 13:03 ` Thomas Gleixner [this message]
2025-06-12 14:38 ` Vladimir Kondratiev
2025-06-10 10:05 ` [PATCH v2 5/7] irqchip: aslint-sswi: resolve hart index Vladimir Kondratiev
2025-06-10 10:05 ` [PATCH v2 6/7] irqchip: aclint-sswi: reduce data scope Vladimir Kondratiev
2025-06-10 10:05 ` [PATCH v2 7/7] irqchip: aclint-sswi: remove extra includes Vladimir Kondratiev
2025-06-12 14:39 ` [PATCH v3 0/7] MIPS P8700 variant of the ACLINT IPI controller Vladimir Kondratiev
2025-06-12 14:39 ` [PATCH v3 1/7] riscv: helper to parse hart index Vladimir Kondratiev
2025-06-20 19:31 ` Thomas Gleixner
2025-06-12 14:39 ` [PATCH v3 2/7] irqchip/riscv-aplic: use riscv_get_hart_index() Vladimir Kondratiev
2025-06-12 14:39 ` [PATCH v3 3/7] dt-bindings: interrupt-controller: add MIPS P8700 aclint-sswi Vladimir Kondratiev
2025-06-12 15:35 ` Conor Dooley
2025-06-12 14:39 ` [PATCH v3 4/7] irqchip: MIPS P800 variant of aclint-sswi Vladimir Kondratiev
2025-06-12 14:39 ` [PATCH v3 5/7] irqchip/aslint-sswi: resolve hart index Vladimir Kondratiev
2025-06-12 14:39 ` [PATCH v3 6/7] irqchip/aclint-sswi: reduce data scope Vladimir Kondratiev
2025-06-12 14:39 ` [PATCH v3 7/7] irqchip/aclint-sswi: remove extra includes Vladimir Kondratiev
2025-06-26 13:48 ` [PATCH v3 0/7] MIPS P8700 variant of the ACLINT IPI controller Thomas Gleixner
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