From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: "Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Saravana Kannan" <saravanak@google.com>,
"Anup Patel" <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
"Anup Patel" <apatel@ventanamicro.com>
Subject: Re: [PATCH v11 08/14] irqchip/riscv-imsic: Add support for platform MSI irqdomain
Date: Wed, 25 Oct 2023 21:56:47 +0200 [thread overview]
Message-ID: <87edhi5vcw.ffs@tglx> (raw)
In-Reply-To: <20231023172800.315343-9-apatel@ventanamicro.com>
On Mon, Oct 23 2023 at 22:57, Anup Patel wrote:
> The Linux platform MSI support requires a platform MSI irqdomain so
> let us add a platform irqchip driver for RISC-V IMSIC which provides
> a base IRQ domain and platform MSI domain. This driver assumes that
> the IMSIC state is already initialized by the IMSIC early driver.
Please no. The platform MSI cruft is really a horrible concept and there
is ongoing work (sadly mightily delayed) to convert the main (ab)user
ARM over to per device MSI domains.
https://lore.kernel.org/r/20221121135653.208611233@linutronix.de
next prev parent reply other threads:[~2023-10-25 19:56 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 17:27 [PATCH v11 00/14] Linux RISC-V AIA Support Anup Patel
2023-10-23 17:27 ` [PATCH v11 01/14] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-10-24 11:55 ` Björn Töpel
2023-10-24 12:07 ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 02/14] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-10-23 17:27 ` [PATCH v11 03/14] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Anup Patel
2023-10-23 17:27 ` [PATCH v11 04/14] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2023-10-23 17:27 ` [PATCH v11 05/14] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-10-24 12:17 ` Andrew Jones
2023-10-23 17:27 ` [PATCH v11 06/14] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-10-24 12:30 ` Andrew Jones
2023-10-23 17:27 ` [PATCH v11 07/14] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-10-24 9:25 ` Conor Dooley
2023-10-24 12:08 ` Anup Patel
2023-10-24 13:05 ` Björn Töpel
2023-10-25 5:08 ` Anup Patel
2023-10-25 16:05 ` Björn Töpel
2023-10-25 17:25 ` Anup Patel
2023-10-26 8:51 ` Björn Töpel
2023-10-28 18:18 ` Thomas Gleixner
2023-10-28 18:34 ` Thomas Gleixner
2023-10-23 17:27 ` [PATCH v11 08/14] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-10-25 19:56 ` Thomas Gleixner [this message]
2023-10-23 17:27 ` [PATCH v11 09/14] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-10-24 13:09 ` Björn Töpel
2023-10-25 5:08 ` Anup Patel
2023-10-25 8:55 ` Björn Töpel
2023-10-28 18:36 ` Thomas Gleixner
2023-10-29 19:53 ` Björn Töpel
2023-10-25 19:59 ` Thomas Gleixner
2023-10-23 17:27 ` [PATCH v11 10/14] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-10-23 17:27 ` [PATCH v11 11/14] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-10-23 17:27 ` [PATCH v11 12/14] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-10-24 5:31 ` Sunil V L
2023-11-02 6:38 ` Ben
[not found] ` <210e2757.3169.18b8eb4495c.Coremail.figure1802@126.com>
2023-11-02 12:37 ` [PATCH " Anup Patel
2023-11-03 9:39 ` Ben
2023-11-03 11:04 ` Anup Patel
2023-11-04 0:58 ` Ben
2023-11-08 14:20 ` Ben
2023-11-08 14:43 ` [PATCH " Anup Patel
2023-11-08 14:51 ` Ben
2023-11-08 14:56 ` Anup Patel
2023-11-08 15:32 ` Ben
2023-11-14 9:21 ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 13/14] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-10-23 17:28 ` [PATCH v11 14/14] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87edhi5vcw.ffs@tglx \
--to=tglx@linutronix.de \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=apatel@ventanamicro.com \
--cc=atishp@atishpatra.org \
--cc=bjorn@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=saravanak@google.com \
--cc=sunilvl@ventanamicro.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).