From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92A6FC43460 for ; Thu, 29 Apr 2021 07:40:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E73D61441 for ; Thu, 29 Apr 2021 07:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233375AbhD2Hll convert rfc822-to-8bit (ORCPT ); Thu, 29 Apr 2021 03:41:41 -0400 Received: from mail.kernel.org ([198.145.29.99]:39164 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231889AbhD2Hld (ORCPT ); Thu, 29 Apr 2021 03:41:33 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 093BB613BD; Thu, 29 Apr 2021 07:40:47 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lc1Hw-009zNf-QY; Thu, 29 Apr 2021 08:40:44 +0100 Date: Thu, 29 Apr 2021 08:40:43 +0100 Message-ID: <87eeeto7wk.wl-maz@kernel.org> From: Marc Zyngier To: =?UTF-8?B?6ZmI5Lqu?= Cc: heiko@sntech.de, robh+dt@kernel.org, jagan@amarulasolutions.com, wens@csie.org, uwe@kleine-koenig.org, mail@david-bauer.net, jbx6244@gmail.com, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, jensenhuang@friendlyarm.com, michael@amarulasolutions.com, cnsztl@gmail.com, devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, linux-i2c@vger.kernel.org, jay.xu@rock-chips.com, shawn.lin@rock-chips.com, david.wu@rock-chips.com, zhangqing@rock-chips.com, huangtao@rock-chips.com, wim@linux-watchdog.org, linux@roeck-us.net, jamie@jamieiles.com, linux-watchdog@vger.kernel.org Subject: Re: [PATCH v3 09/10] arm64: dts: rockchip: add core dtsi for RK3568 SoC In-Reply-To: <3401442c-24a1-e8f8-fc4a-fa44d94b903b@rock-chips.com> References: <20210428134759.22076-1-cl@rock-chips.com> <20210428135002.22528-1-cl@rock-chips.com> <87h7jqo3d2.wl-maz@kernel.org> <3401442c-24a1-e8f8-fc4a-fa44d94b903b@rock-chips.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: cl@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, jagan@amarulasolutions.com, wens@csie.org, uwe@kleine-koenig.org, mail@david-bauer.net, jbx6244@gmail.com, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, jensenhuang@friendlyarm.com, michael@amarulasolutions.com, cnsztl@gmail.com, devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, linux-i2c@vger.kernel.org, jay.xu@rock-chips.com, shawn.lin@rock-chips.com, david.wu@rock-chips.com, zhangqing@rock-chips.com, huangtao@rock-chips.com, wim@linux-watchdog.org, linux@roeck-us.net, jamie@jamieiles.com, linux-watchdog@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 29 Apr 2021 02:13:35 +0100, 陈亮 wrote: > > Hi Marc, > > 在 2021/4/28 下午11:06, Marc Zyngier 写道: > > On Wed, 28 Apr 2021 14:50:02 +0100, > > wrote: > >> From: Liang Chen > >> > >> RK3568 is a high-performance and low power quad-core application processor > >> designed for personal mobile internet device and AIoT equipment. This patch > >> add basic core dtsi file for it. > >> > >> We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that > >> kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will > >> enalbe a special high-performance PLL when high frequency is required. The > >> smci_clk code is in ATF, and clkid for cpu is 0, as below: > >> > >> cpu0: cpu@0 { > >> device_type = "cpu"; > >> compatible = "arm,cortex-a55"; > >> reg = <0x0 0x0>; > >> clocks = <&scmi_clk 0>; > >> }; > >> > >> Signed-off-by: Liang Chen > >> --- > >> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3111 +++++++++++++++++ > >> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 779 +++++ > >> 2 files changed, 3890 insertions(+) > >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > >> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi > > [...] > > > >> + gic: interrupt-controller@fd400000 { > >> + compatible = "arm,gic-v3"; > >> + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ > >> + <0x0 0xfd460000 0 0xc0000>; /* GICR */ > > If this SoC has 4 CPUs, that's 4 redistributors. Given that GIC600 > > doesn't implement VLPIs, that's 128kB per redistributors. Why is GICR > > large enough for 6 CPUs here? Is that copy-pasted from another SoC? > Copy from rk3399, sorry. > >> + interrupts = ; > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + mbi-alias = <0x0 0xfd400000>; > >> + mbi-ranges = <296 24>; > >> + msi-controller; > >> + }; > > Glad to see that you found some spare SPIs to get MSIs going > > > > However, the whole point of mbi-alias (aka GICA in GIC600) is to be > > different from GICD and provide some isolation via an IOMMU. If I > > trust the TRM, if should be at 0xfd10000 in your implementation. > > But in the ./devicetree/bindings/interrupt-controller/arm,gic-v3.yaml, say: > >   mbi-alias: >     description: >       Address property. Base address of an alias of the *GICD* region > containing >       only the {SET,CLR}SPI registers to be used if isolation is required, >       and if supported by the HW. [recurring theme: I happen to know about this section of the binding, having written the original myself] How does that contradict my comment? GIC600's GICA page only contains the four {SET,CLR}_SPI registers, as expected (see section 4.3 in the TRM[1]), and the address is computed using table 4-1 "Register map pages" of the same document. Please either fix the DT or explain why the GICA distributor alias isn't usable. M. [1] https://documentation-service.arm.com/static/5e7ddddacbfe76649ba53034 -- Without deviation from the norm, progress is not possible.