From: Thomas Gleixner <tglx@linutronix.de>
To: Herve Codina <herve.codina@bootlin.com>,
Simon Horman <horms@kernel.org>,
Sai Krishna Gajula <saikrishnag@marvell.com>,
Herve Codina <herve.codina@bootlin.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Lee Jones <lee@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Horatiu Vultur <horatiu.vultur@microchip.com>,
UNGLinuxDriver@microchip.com, Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Saravana Kannan <saravanak@google.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Lars Povlsen <lars.povlsen@microchip.com>,
Steen Hegelund <Steen.Hegelund@microchip.com>,
Daniel Machon <daniel.machon@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
netdev@vger.kernel.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Allan Nielsen <allan.nielsen@microchip.com>,
Steen Hegelund <steen.hegelund@microchip.com>,
Luca Ceresoli <luca.ceresoli@bootlin.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH v2 11/19] irqchip: Add support for LAN966x OIC
Date: Wed, 05 Jun 2024 16:17:53 +0200 [thread overview]
Message-ID: <87frtr4goe.ffs@tglx> (raw)
In-Reply-To: <20240527161450.326615-12-herve.codina@bootlin.com>
On Mon, May 27 2024 at 18:14, Herve Codina wrote:
> +struct lan966x_oic_data {
> + struct irq_domain *domain;
> + void __iomem *regs;
> + int irq;
> +};
Please read Documentation/process/maintainers-tip.rst
> +static int lan966x_oic_irq_set_type(struct irq_data *data,
> + unsigned int flow_type)
Please use the 100 character limit
> +static struct lan966x_oic_chip_regs lan966x_oic_chip_regs[3] = {
> + {
> + .reg_off_ena_set = LAN966X_OIC_INTR_ENA_SET,
> + .reg_off_ena_clr = LAN966X_OIC_INTR_ENA_CLR,
> + .reg_off_sticky = LAN966X_OIC_INTR_STICKY,
> + .reg_off_ident = LAN966X_OIC_DST_INTR_IDENT(0),
> + .reg_off_map = LAN966X_OIC_DST_INTR_MAP(0),
Please make this tabular. See doc.
> +static void lan966x_oic_chip_init(struct lan966x_oic_data *lan966x_oic,
> + struct irq_chip_generic *gc,
> + struct lan966x_oic_chip_regs *chip_regs)
> +{
> + gc->reg_base = lan966x_oic->regs;
> + gc->chip_types[0].regs.enable = chip_regs->reg_off_ena_set;
> + gc->chip_types[0].regs.disable = chip_regs->reg_off_ena_clr;
> + gc->chip_types[0].regs.ack = chip_regs->reg_off_sticky;
> + gc->chip_types[0].chip.irq_startup = lan966x_oic_irq_startup;
> + gc->chip_types[0].chip.irq_shutdown = lan966x_oic_irq_shutdown;
> + gc->chip_types[0].chip.irq_set_type = lan966x_oic_irq_set_type;
> + gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
> + gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
> + gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
> + gc->private = chip_regs;
> +
> + /* Disable all interrupts handled by this chip */
> + irq_reg_writel(gc, ~0, chip_regs->reg_off_ena_clr);
> +}
> +
> +static void lan966x_oic_chip_exit(struct irq_chip_generic *gc)
> +{
> + /* Disable and ack all interrupts handled by this chip */
> + irq_reg_writel(gc, ~0, gc->chip_types[0].regs.disable);
~0U
> + irq_reg_writel(gc, ~0, gc->chip_types[0].regs.ack);
> +}
> +
> +static int lan966x_oic_probe(struct platform_device *pdev)
> +{
> + struct device_node *node = pdev->dev.of_node;
> + struct lan966x_oic_data *lan966x_oic;
> + struct device *dev = &pdev->dev;
> + struct irq_chip_generic *gc;
> + int ret;
> + int i;
int ret, i;
> +
> + lan966x_oic = devm_kmalloc(dev, sizeof(*lan966x_oic), GFP_KERNEL);
> + if (!lan966x_oic)
> + return -ENOMEM;
> +
> + lan966x_oic->regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(lan966x_oic->regs))
> + return dev_err_probe(dev, PTR_ERR(lan966x_oic->regs),
> + "failed to map resource\n");
> +
> + lan966x_oic->domain = irq_domain_alloc_linear(of_node_to_fwnode(node),
> + LAN966X_OIC_NR_IRQ,
> + &irq_generic_chip_ops,
> + NULL);
> + if (!lan966x_oic->domain) {
> + dev_err(dev, "failed to create an IRQ domain\n");
> + return -EINVAL;
> + }
> +
> + lan966x_oic->irq = platform_get_irq(pdev, 0);
> + if (lan966x_oic->irq < 0) {
> + ret = dev_err_probe(dev, lan966x_oic->irq,
> + "failed to get the IRQ\n");
> + goto err_domain_free;
> + }
> +
> + ret = irq_alloc_domain_generic_chips(lan966x_oic->domain, 32, 1,
> + "lan966x-oic", handle_level_irq, 0,
> + 0, 0);
> + if (ret) {
> + dev_err_probe(dev, ret, "failed to alloc irq domain gc\n");
> + goto err_domain_free;
> + }
> +
> + /* Init chips */
> + BUILD_BUG_ON(DIV_ROUND_UP(LAN966X_OIC_NR_IRQ, 32) !=
> + ARRAY_SIZE(lan966x_oic_chip_regs));
> + for (i = 0; i < ARRAY_SIZE(lan966x_oic_chip_regs); i++) {
> + gc = irq_get_domain_generic_chip(lan966x_oic->domain, i * 32);
> + lan966x_oic_chip_init(lan966x_oic, gc,
> + &lan966x_oic_chip_regs[i]);
> + }
> +
> + irq_set_chained_handler_and_data(lan966x_oic->irq,
> + lan966x_oic_irq_handler,
> + lan966x_oic->domain);
> +
> + irq_domain_publish(lan966x_oic->domain);
> + platform_set_drvdata(pdev, lan966x_oic);
> + return 0;
This is exactly what can be avoided.
> +
> +err_domain_free:
> + irq_domain_free(lan966x_oic->domain);
> + return ret;
> +}
> +
> +static void lan966x_oic_remove(struct platform_device *pdev)
> +{
> + struct lan966x_oic_data *lan966x_oic = platform_get_drvdata(pdev);
> + struct irq_chip_generic *gc;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(lan966x_oic_chip_regs); i++) {
> + gc = irq_get_domain_generic_chip(lan966x_oic->domain, i * 32);
> + lan966x_oic_chip_exit(gc);
> + }
> +
> + irq_set_chained_handler_and_data(lan966x_oic->irq, NULL, NULL);
> +
> + for (i = 0; i < LAN966X_OIC_NR_IRQ; i++)
> + irq_dispose_mapping(irq_find_mapping(lan966x_oic->domain, i));
This is just wrong. You cannot remove the chip when there are still interrupts
mapped.
I just did a quick conversion to the template approach. Unsurprisingly
it removes 30 lines of boiler plate code:
+static void lan966x_oic_chip_init(struct irq_chip_generic *gc)
+{
+ struct lan966x_oic_data *lan966x_oic = gc->domain->host_data;
+ struct lan966x_oic_chip_regs *chip_regs;
+
+ gc->reg_base = lan966x_oic->regs;
+
+ chip_regs = lan966x_oic_chip_regs + gc->irq_base / 32;
+ gc->chip_types[0].regs.enable = chip_regs->reg_off_ena_set;
+ gc->chip_types[0].regs.disable = chip_regs->reg_off_ena_clr;
+ gc->chip_types[0].regs.ack = chip_regs->reg_off_sticky;
+
+ gc->chip_types[0].chip.irq_startup = lan966x_oic_irq_startup;
+ gc->chip_types[0].chip.irq_shutdown = lan966x_oic_irq_shutdown;
+ gc->chip_types[0].chip.irq_set_type = lan966x_oic_irq_set_type;
+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
+ gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
+ gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
+ gc->private = chip_regs;
+
+ /* Disable all interrupts handled by this chip */
+ irq_reg_writel(gc, ~0, chip_regs->reg_off_ena_clr);
+}
+
+static void lan966x_oic_chip_exit(struct irq_chip_generic *gc)
+{
+ /* Disable and ack all interrupts handled by this chip */
+ irq_reg_writel(gc, ~0, gc->chip_types[0].regs.disable);
+ irq_reg_writel(gc, ~0, gc->chip_types[0].regs.ack);
+}
+
+static void lan966x_oic_domain_init(struct irq_domain *d)
+{
+ struct lan966x_oic_data *lan966x_oic = d->host_data;
+
+ irq_set_chained_handler_and_data(lan966x_oic->irq, lan966x_oic_irq_handler, d);
+}
+
+static int lan966x_oic_probe(struct platform_device *pdev)
+{
+ struct irq_domain_chip_generic_info gc_info = {
+ .irqs_per_chip = 32,
+ .num_chips = 1,
+ .name = "lan966x-oic"
+ .handler = handle_level_irq,
+ .init = lan966x_oic_chip_init,
+ .destroy = lan966x_oic_chip_exit,
+ };
+
+ struct irq_domain_info info = {
+ .fwnode = of_node_to_fwnode(pdev->dev.of_node),
+ .size = LAN966X_OIC_NR_IRQ,
+ .hwirq_max = LAN966X_OIC_NR_IRQ,
+ .ops = &irq_generic_chip_ops,
+ .gc_info = &gc_info,
+ .init = lan966x_oic_domain_init,
+ };
+ struct lan966x_oic_data *lan966x_oic;
+ struct device *dev = &pdev->dev;
+
+ lan966x_oic = devm_kmalloc(dev, sizeof(*lan966x_oic), GFP_KERNEL);
+ if (!lan966x_oic)
+ return -ENOMEM;
+
+ lan966x_oic->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(lan966x_oic->regs))
+ return dev_err_probe(dev, PTR_ERR(lan966x_oic->regs), "failed to map resource\n");
+
+ lan966x_oic->irq = platform_get_irq(pdev, 0);
+ if (lan966x_oic->irq < 0)
+ return dev_err_probe(dev, lan966x_oic->irq, "failed to get the IRQ\n");
+
+ lan966x_oic->domain = irq_domain_instantiate(&info);
+ if (!lan966x_oic->domain)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, lan966x_oic);
+ return 0;
+}
+
+static void lan966x_oic_remove(struct platform_device *pdev)
+{
+ struct lan966x_oic_data *lan966x_oic = platform_get_drvdata(pdev);
+
+ irq_set_chained_handler_and_data(lan966x_oic->irq, NULL, NULL);
+ irq_domain_remove(lan966x_oic->domain);
+}
See?
Thanks,
tglx
next prev parent reply other threads:[~2024-06-05 14:17 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-27 16:14 [PATCH v2 00/19] Add support for the LAN966x PCI device using a DT overlay Herve Codina
2024-05-27 16:14 ` [PATCH v2 01/19] mfd: syscon: Add reference counting and device managed support Herve Codina
2024-06-18 14:53 ` Arnd Bergmann
2024-06-18 15:55 ` Herve Codina
2024-05-27 16:14 ` [PATCH v2 02/19] reset: mchp: sparx5: Remove dependencies and allow building as a module Herve Codina
2024-05-27 16:14 ` [PATCH v2 03/19] reset: mchp: sparx5: Release syscon when not use anymore Herve Codina
2024-05-27 16:14 ` [PATCH v2 04/19] reset: core: add get_device()/put_device on rcdev Herve Codina
2024-05-27 16:14 ` [PATCH v2 05/19] reset: mchp: sparx5: set the dev member of the reset controller Herve Codina
2024-05-27 16:14 ` [PATCH v2 06/19] dt-bindings: net: mscc-miim: Add resets property Herve Codina
2024-05-27 19:14 ` Andrew Lunn
2024-05-28 6:44 ` Krzysztof Kozlowski
2024-05-27 16:14 ` [PATCH v2 07/19] net: mdio: mscc-miim: Handle the switch reset Herve Codina
2024-05-27 19:16 ` Andrew Lunn
2024-05-27 16:14 ` [PATCH v2 08/19] dt-bindings: interrupt-controller: Add support for Microchip LAN966x OIC Herve Codina
2024-05-27 16:14 ` [PATCH v2 09/19] irqdomain: Add missing parameter descriptions in docs Herve Codina
2024-06-04 19:02 ` Thomas Gleixner
2024-06-05 20:02 ` Andy Shevchenko
2024-06-06 7:14 ` Herve Codina
2024-06-06 8:46 ` Andy Shevchenko
2024-06-06 10:16 ` Herve Codina
2024-05-27 16:14 ` [PATCH v2 10/19] irqdomain: Introduce irq_domain_alloc() and irq_domain_publish() Herve Codina
2024-06-04 19:59 ` Thomas Gleixner
2024-06-05 13:02 ` Thomas Gleixner
2024-06-06 15:52 ` Herve Codina
2024-06-06 18:11 ` Thomas Gleixner
2024-06-07 8:06 ` Herve Codina
2024-05-27 16:14 ` [PATCH v2 11/19] irqchip: Add support for LAN966x OIC Herve Codina
2024-06-05 14:17 ` Thomas Gleixner [this message]
2024-06-05 20:14 ` Andy Shevchenko
2024-06-06 15:53 ` Herve Codina
2024-05-27 16:14 ` [PATCH v2 12/19] MAINTAINERS: Add the Microchip LAN966x OIC driver entry Herve Codina
2024-05-27 16:14 ` [PATCH v2 13/19] of: dynamic: Constify parameter in of_changeset_add_prop_string_array() Herve Codina
2024-05-27 16:14 ` [PATCH v2 14/19] of: unittest: Add tests for changeset properties adding Herve Codina
2024-05-27 16:14 ` [PATCH v2 15/19] of: dynamic: Introduce of_changeset_add_prop_bool() Herve Codina
2024-05-27 16:14 ` [PATCH v2 16/19] of: unittest: Add a test case for of_changeset_add_prop_bool() Herve Codina
2024-05-27 16:14 ` [PATCH v2 17/19] PCI: of_property: Add interrupt-controller property in PCI device nodes Herve Codina
2024-06-06 19:26 ` Bjorn Helgaas
2024-06-10 21:37 ` Rob Herring
2024-06-11 17:13 ` Bjorn Helgaas
2024-05-27 16:14 ` [PATCH v2 18/19] mfd: Add support for LAN966x PCI device Herve Codina
2024-06-05 20:24 ` Andy Shevchenko
[not found] ` <20240620175646.24455efb@bootlin.com>
2024-06-20 16:43 ` Herve Codina
[not found] ` <CAHp75VdDkv-dxWa60=OLfXAQ8T5CkFiKALbDHaVVKQOK3gJehA@mail.gmail.com>
2024-06-20 16:43 ` Herve Codina
2024-06-20 17:19 ` Herve Codina
2024-06-21 15:45 ` Andy Shevchenko
2024-06-21 18:49 ` Bjorn Helgaas
2024-06-24 11:46 ` Steen Hegelund
2024-06-26 6:52 ` Herve Codina
2024-06-26 7:17 ` Steen Hegelund
2024-06-24 8:20 ` Herve Codina
2024-06-05 21:34 ` Bjorn Helgaas
2024-05-27 16:14 ` [PATCH v2 19/19] MAINTAINERS: Add the Microchip LAN966x PCI driver entry Herve Codina
2024-05-30 0:08 ` [PATCH v2 00/19] Add support for the LAN966x PCI device using a DT overlay Jakub Kicinski
2024-06-11 19:33 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87frtr4goe.ffs@tglx \
--to=tglx@linutronix.de \
--cc=Steen.Hegelund@microchip.com \
--cc=UNGLinuxDriver@microchip.com \
--cc=alexandre.belloni@bootlin.com \
--cc=allan.nielsen@microchip.com \
--cc=andrew@lunn.ch \
--cc=arnd@arndb.de \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=daniel.machon@microchip.com \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=edumazet@google.com \
--cc=herve.codina@bootlin.com \
--cc=hkallweit1@gmail.com \
--cc=horatiu.vultur@microchip.com \
--cc=horms@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=kuba@kernel.org \
--cc=lars.povlsen@microchip.com \
--cc=lee@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=luca.ceresoli@bootlin.com \
--cc=netdev@vger.kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=pabeni@redhat.com \
--cc=robh@kernel.org \
--cc=saikrishnag@marvell.com \
--cc=saravanak@google.com \
--cc=thomas.petazzoni@bootlin.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).