From: Marc Zyngier <maz@kernel.org>
To: Rui Miguel Silva <rui.silva@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree
Date: Mon, 28 Mar 2022 17:35:34 +0100 [thread overview]
Message-ID: <87fsn2f31l.wl-maz@kernel.org> (raw)
In-Reply-To: <20220325133655.4177977-3-rui.silva@linaro.org>
On Fri, 25 Mar 2022 13:36:55 +0000,
Rui Miguel Silva <rui.silva@linaro.org> wrote:
>
> Corstone1000 is a platform from arm, which includes pre
> verified Corstone SSE710 sub-system that combines Cortex-A and
> Cortex-M processors [0].
>
> These device trees contains the necessary bits to support the
> Corstone 1000 FVP (Fixed Virtual Platform) [1] and the
> FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host
> side of this platform. [2]
>
> 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16
> 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
> 2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf
>
> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
> ---
> arch/arm64/boot/dts/arm/Makefile | 1 +
> arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 31 ++++
> arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 38 +++++
> arch/arm64/boot/dts/arm/corstone1000.dtsi | 151 ++++++++++++++++++
> 4 files changed, 221 insertions(+)
> create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts
> create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi
>
> diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
> index 4382b73baef5..d908e96d7ddc 100644
> --- a/arch/arm64/boot/dts/arm/Makefile
> +++ b/arch/arm64/boot/dts/arm/Makefile
> @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju
> dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
> dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
> dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
> +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
> diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> new file mode 100644
> index 000000000000..8f6ce94b4d5a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2022, Arm Limited. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited. All rights reserved.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "corstone1000.dtsi"
> +
> +/ {
> + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
> + compatible = "arm,corstone1000-fvp";
> +
> + ethernet: eth@4010000 {
> + compatible = "smsc,lan91c111";
> + reg = <0x40100000 0x10000>;
> + phy-mode = "mii";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 116 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
-ENOPARSE. Please read the GIC binding.
> + reg-io-width = <2>;
> + smsc,irq-push-pull;
> + };
> +
> +};
> +
> +&refclk {
> + clock-frequency = <50000000>;
> +};
> diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
> new file mode 100644
> index 000000000000..922253f0af07
> --- /dev/null
> +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
[...]
> + gic: interrupt-controller@1c000000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x1c010000 0x1000>,
> + <0x1c02f000 0x2000>,
> + <0x1c04f000 0x1000>,
> + <0x1c06f000 0x2000>;
> + interrupts = <1 9 0xf08>;
Why 4 CPUs? You only have 1. The rest of the file seems to use the
symbolic encoding, so please pick one or the other, but don't mix
them.
[...]
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_LOW)>;
Same question.
> + };
> +
> + refclk: refclk@1a220000 {
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x1a220000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + frame@1a230000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 2 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
This makes no sense either.
M.
--
Without deviation from the norm, progress is not possible.
prev parent reply other threads:[~2022-03-28 16:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-25 13:36 [PATCH 0/2] arm64: dts: add corstone1000 device tree Rui Miguel Silva
2022-03-25 13:36 ` [PATCH 1/2] dt-bindings: arm: add corstone1000 platform Rui Miguel Silva
2022-03-25 17:29 ` Krzysztof Kozlowski
2022-03-28 16:19 ` Rob Herring
2022-03-25 17:34 ` Krzysztof Kozlowski
2022-03-25 13:36 ` [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree Rui Miguel Silva
2022-03-25 17:46 ` Rob Herring
2022-03-28 16:35 ` Marc Zyngier [this message]
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