From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2ABCC433EF for ; Mon, 28 Mar 2022 16:35:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242478AbiC1QhT (ORCPT ); Mon, 28 Mar 2022 12:37:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233943AbiC1QhS (ORCPT ); Mon, 28 Mar 2022 12:37:18 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C7F2606E3 for ; Mon, 28 Mar 2022 09:35:38 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A5AEE61483 for ; Mon, 28 Mar 2022 16:35:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C4AEC004DD; Mon, 28 Mar 2022 16:35:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1648485337; bh=Bll15YJCV3NEHAf9DjC+S6pLaySgAtZIx1YauCjLUNg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=deOmDomAaTxuOWT4w3CGnQlR/kV7/ANe+58LVWpO2Z0jrkrLoK0Z7LlNVncjRn+aK NRWaEKMykFH5A6/cb64cJe6r6KVSbz6gBYi3C3TQyZfmMZjTlrOz5Inex8r5K7VNb4 KZwhPtyXiSbaCA1qgbKDmf0JC05alu0Z3rNpcbBgluzf2FuLwIO5RKzx/58YD+yM5a J4f/Ole5LSjbMlDo9jIpg+F+NU86t60QBZPTcdXNZE451YWj8MatCR58nt4zhKLKqR +79DsNPHd9/fh+AGmeDlp+LWhcNAX5pAi07mEfE2KCNpQS620U3iFgxI8Y4zzL4zRz CycjD235jbhFA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nYsL8-00HT5p-Gs; Mon, 28 Mar 2022 17:35:34 +0100 Date: Mon, 28 Mar 2022 17:35:34 +0100 Message-ID: <87fsn2f31l.wl-maz@kernel.org> From: Marc Zyngier To: Rui Miguel Silva Cc: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: dts: arm: add corstone1000 device tree In-Reply-To: <20220325133655.4177977-3-rui.silva@linaro.org> References: <20220325133655.4177977-1-rui.silva@linaro.org> <20220325133655.4177977-3-rui.silva@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: rui.silva@linaro.org, liviu.dudau@arm.com, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, 25 Mar 2022 13:36:55 +0000, Rui Miguel Silva wrote: > > Corstone1000 is a platform from arm, which includes pre > verified Corstone SSE710 sub-system that combines Cortex-A and > Cortex-M processors [0]. > > These device trees contains the necessary bits to support the > Corstone 1000 FVP (Fixed Virtual Platform) [1] and the > FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host > side of this platform. [2] > > 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16 > 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps > 2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf > > Signed-off-by: Rui Miguel Silva > --- > arch/arm64/boot/dts/arm/Makefile | 1 + > arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 31 ++++ > arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 38 +++++ > arch/arm64/boot/dts/arm/corstone1000.dtsi | 151 ++++++++++++++++++ > 4 files changed, 221 insertions(+) > create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts > create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts > create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi > > diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile > index 4382b73baef5..d908e96d7ddc 100644 > --- a/arch/arm64/boot/dts/arm/Makefile > +++ b/arch/arm64/boot/dts/arm/Makefile > @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb > dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb > +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb > diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts > new file mode 100644 > index 000000000000..8f6ce94b4d5a > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022, Arm Limited. All rights reserved. > + * Copyright (c) 2022, Linaro Limited. All rights reserved. > + * > + */ > + > +/dts-v1/; > + > +#include "corstone1000.dtsi" > + > +/ { > + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; > + compatible = "arm,corstone1000-fvp"; > + > + ethernet: eth@4010000 { > + compatible = "smsc,lan91c111"; > + reg = <0x40100000 0x10000>; > + phy-mode = "mii"; > + interrupt-parent = <&gic>; > + interrupts = + IRQ_TYPE_LEVEL_HIGH)>; -ENOPARSE. Please read the GIC binding. > + reg-io-width = <2>; > + smsc,irq-push-pull; > + }; > + > +}; > + > +&refclk { > + clock-frequency = <50000000>; > +}; > diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts > new file mode 100644 > index 000000000000..922253f0af07 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts [...] > + gic: interrupt-controller@1c000000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x1c010000 0x1000>, > + <0x1c02f000 0x2000>, > + <0x1c04f000 0x1000>, > + <0x1c06f000 0x2000>; > + interrupts = <1 9 0xf08>; Why 4 CPUs? You only have 1. The rest of the file seems to use the symbolic encoding, so please pick one or the other, but don't mix them. [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = + IRQ_TYPE_LEVEL_LOW)>, > + + IRQ_TYPE_LEVEL_LOW)>, > + + IRQ_TYPE_LEVEL_LOW)>, > + + IRQ_TYPE_LEVEL_LOW)>; Same question. > + }; > + > + refclk: refclk@1a220000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x1a220000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + frame@1a230000 { > + frame-number = <0>; > + interrupts = + IRQ_TYPE_LEVEL_HIGH)>; This makes no sense either. M. -- Without deviation from the norm, progress is not possible.