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Mon, 13 Jul 2026 15:16:11 +0000 Date: Mon, 13 Jul 2026 16:18:00 +0100 Message-ID: <87h5m26hqv.wl-maz@kernel.org> From: Marc Zyngier To: Sneh Mankad Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Shawn Guo , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/7] irqchip/irq-qcom-mpm: Program wakeup timer when CPU cluster goes to LPM In-Reply-To: <20260713-b4-shikra_lpm_addition-v1-4-3d858df2cbbf@oss.qualcomm.com> References: <20260713-b4-shikra_lpm_addition-v1-0-3d858df2cbbf@oss.qualcomm.com> <20260713-b4-shikra_lpm_addition-v1-4-3d858df2cbbf@oss.qualcomm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sneh.mankad@oss.qualcomm.com, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tglx@kernel.org, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 13 Jul 2026 11:25:44 +0100, Sneh Mankad wrote: > > The next wakeup timer value needs to be set in MPM timer as the arch timer > interrupt can not wakeup the SoC if after the deepest CPUidle states the > SoC also enters deepest low power state. > > To wakeup the SoC in such scenarios the earliest wakeup time is set in MPM > timer and the Resource Power Manager (RPM processor) takes care of setting > the timer in HW. > > Add MPM timer programming when CPU cluster enters power collapse. > > Signed-off-by: Sneh Mankad > --- > drivers/irqchip/irq-qcom-mpm.c | 44 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c > index 763eddee99dc4cdd5edab22ce54808528f9ef165..f43c4a1c35f78b6cdae194dc7ae88c5c307ada94 100644 > --- a/drivers/irqchip/irq-qcom-mpm.c > +++ b/drivers/irqchip/irq-qcom-mpm.c > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -25,6 +26,8 @@ > #include > #include > > +#include > + > /* > * This is the driver for Qualcomm MPM (MSM Power Manager) interrupt controller, > * which is commonly found on Qualcomm SoCs built on the RPM architecture. > @@ -77,6 +80,13 @@ enum qcom_mpm_reg { > MPM_REG_STATUS, > }; > > +#define USECS_TO_CYCLES(time_usecs) xloops_to_cycles((time_usecs) * 0x10C7UL) > + > +static inline unsigned long xloops_to_cycles(u64 xloops) > +{ > + return (xloops * loops_per_jiffy * HZ) >> 32; > +} > + Do we really need arch-specific code to be literally copied from arm64's delay.c, without any comment or attempt at making it generic? Specially after having added the same stuff to rpmh-rsc.c 4 years ago? See a pattern here? M. -- Jazz isn't dead. It just smells funny.