From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31618C433ED for ; Mon, 17 May 2021 09:21:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1328C61042 for ; Mon, 17 May 2021 09:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235842AbhEQJXL convert rfc822-to-8bit (ORCPT ); Mon, 17 May 2021 05:23:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:42530 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235984AbhEQJXK (ORCPT ); Mon, 17 May 2021 05:23:10 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 101DD61042; Mon, 17 May 2021 09:21:07 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1liZQv-001lcC-0U; Mon, 17 May 2021 10:21:05 +0100 Date: Mon, 17 May 2021 10:21:04 +0100 Message-ID: <87h7j1vhq7.wl-maz@kernel.org> From: Marc Zyngier To: Andreas =?UTF-8?B?RsOkcmJlcg==?= Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Heiko Stuebner , devicetree@vger.kernel.org Subject: Re: [PATCH 3/9] arm64: dts: rockchip: Prepare Rockchip RK1808 In-Reply-To: <20210516230551.12469-4-afaerber@suse.de> References: <20210516230551.12469-1-afaerber@suse.de> <20210516230551.12469-4-afaerber@suse.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: afaerber@suse.de, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, 17 May 2021 00:05:45 +0100, Andreas Färber wrote: > > Add an initial Device Tree for Rockchip RK1808 SoC. > Based on shipping TB-RK1808M0 DTB. > > Signed-off-by: Andreas Färber > --- > arch/arm64/boot/dts/rockchip/rk1808.dtsi | 203 +++++++++++++++++++++++ > 1 file changed, 203 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk1808.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi > new file mode 100644 > index 000000000000..af2b51afda7d > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi > @@ -0,0 +1,203 @@ > +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) > +/* > + * Copyright (c) 2021 Andreas Färber > + */ > + > +#include > +#include > + > +/ { > + compatible = "rockchip,rk1808"; > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + serial6 = &uart6; > + serial7 = &uart7; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP>; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + CPU_SLEEP: cpu-sleep { > + compatible = "arm,idle-state"; > + local-timer-stop; > + arm,psci-suspend-param = <0x10000>; > + entry-latency-us = <120>; > + exit-latency-us = <250>; > + min-residency-us = <900>; > + }; > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a35-pmu"; > + interrupts = , > + ; > + interrupt-affinity = <&cpu0>, <&cpu1>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + arm,no-tick-in-suspend; Another facepalm moment... > + }; > + > + xin24m: xin24m { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + #clock-cells = <0>; > + clock-output-names = "xin24m"; > + }; > + > + firmware { > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + tee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + system_sram: sram@fec00000 { > + compatible = "mmio-sram"; > + reg = <0xfec00000 0x200000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xfec00000 0x200000>; > + }; > + > + gic: interrupt-controller@ff100000 { > + compatible = "arm,gic-v3"; > + reg = <0xff100000 0x10000>, /* GICD */ > + <0xff140000 0xc0000>, /* GICR */ This is obviously wrong. You have two CPUs, and yet describe a range that spans 6. I guess this is a copy paste from rk3399 again? > + <0xff300000 0x10000>, /* GICC */ > + <0xff310000 0x10000>, /* GICH */ > + <0xff320000 0x10000>; /* GICV */ > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + gic_its: msi-controller@ff120000 { > + compatible = "arm,gic-v3-its"; > + reg = <0xff120000 0x20000>; > + msi-controller; > + #msi-cells = <1>; > + }; What uses the ITS? M. -- Without deviation from the norm, progress is not possible.