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Fri, 12 Sep 2025 14:58:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1757681910; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=6fGibqKE+FAjIZ49uwUJtvQhXhXO0YneIbfrt6lUIe0=; b=eBVMVMl3UH5oHD9LuDgoIy2GiDvmkt/hXSeYR5TRsDwcSzzQIqeZ7fa8W/16Tk0D3A9pZB bkcbZuJfu3QuDFrz8h8PMjzVj67dLPXkyThpVFKVEcX+l1uJWHTelo65UGi9wMrGSf99Cs +0MSUngd9EtG5VlsD3o3aX9pQfPyjWut46To8mYVBoBh/QULATE2gUhufdteISsIb3kFjS XsHIz5UINFa1OrS44PmCUEpA5wzK5vNn8uV+9wCu7heCTqBCLfWBlok6raJIQ06HHfKcrN 0kdgReYhf9PjTBQgEbaM5t3N2ZlJbBvVJ5YWt+5VoxPydJIAOTVV59AwUsF5iQ== From: Gregory CLEMENT To: Josua Mayer , Andrew Lunn , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wunderlich Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Josua Mayer , stable@vger.kernel.org Subject: Re: [PATCH v2 3/4] arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports In-Reply-To: <20250911-cn913x-sr-fix-sata-v2-3-0d79319105f8@solid-run.com> References: <20250911-cn913x-sr-fix-sata-v2-0-0d79319105f8@solid-run.com> <20250911-cn913x-sr-fix-sata-v2-3-0d79319105f8@solid-run.com> Date: Fri, 12 Sep 2025 14:58:29 +0200 Message-ID: <87ikhnomiy.fsf@BLaptop.bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Josua Mayer writes: > The mvebu-comphy driver does not currently know how to pass correct > lane-count to ATF while configuring the serdes lanes. > > This causes the system to hard reset during reconfiguration, if a pci > card is present and has established a link during bootloader. > > Remove the comphy handles from the respective pci nodes to avoid runtime > reconfiguration, relying solely on bootloader configuration - while > avoiding the hard reset. > > When bootloader has configured the lanes correctly, the pci ports are > functional under Linux. > > This issue may be addressed in the comphy driver at a future point. > > Fixes: e9ff907f4076 ("arm64: dts: add description for solidrun cn9132 cex= 7 module and clearfog board") > Cc: > Signed-off-by: Josua Mayer Applied on mvebu/fixes Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/cn9132-clearfog.dts | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64= /boot/dts/marvell/cn9132-clearfog.dts > index 115c55d73786e2b9265e1caa4c62ee26f498fb41..6f237d3542b9102695f8a4845= 7f43340da994a2c 100644 > --- a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts > +++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts > @@ -413,7 +413,13 @@ fixed-link { > /* SRDS #0,#1,#2,#3 - PCIe */ > &cp0_pcie0 { > num-lanes =3D <4>; > - phys =3D <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_co= mphy3 0>; > + /* > + * The mvebu-comphy driver does not currently know how to pass correct > + * lane-count to ATF while configuring the serdes lanes. > + * Rely on bootloader configuration only. > + * > + * phys =3D <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0= _comphy3 0>; > + */ > status =3D "okay"; > }; >=20=20 > @@ -475,7 +481,13 @@ &cp1_eth0 { > /* SRDS #0,#1 - PCIe */ > &cp1_pcie0 { > num-lanes =3D <2>; > - phys =3D <&cp1_comphy0 0>, <&cp1_comphy1 0>; > + /* > + * The mvebu-comphy driver does not currently know how to pass correct > + * lane-count to ATF while configuring the serdes lanes. > + * Rely on bootloader configuration only. > + * > + * phys =3D <&cp1_comphy0 0>, <&cp1_comphy1 0>; > + */ > status =3D "okay"; > }; >=20=20 > > --=20 > 2.51.0 > > --=20 Gr=C3=A9gory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com