From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: "Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Saravana Kannan" <saravanak@google.com>,
"Anup Patel" <anup@brainfault.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
"Anup Patel" <apatel@ventanamicro.com>
Subject: Re: [PATCH v12 14/25] irqchip/sifive-plic: Convert PLIC driver into a platform driver
Date: Fri, 16 Feb 2024 16:33:23 +0100 [thread overview]
Message-ID: <87jzn4ctks.ffs@tglx> (raw)
In-Reply-To: <20240127161753.114685-15-apatel@ventanamicro.com>
On Sat, Jan 27 2024 at 21:47, Anup Patel wrote:
> + priv->irqdomain = irq_domain_create_linear(dev->fwnode, nr_irqs + 1,
> + &plic_irqdomain_ops, priv);
> + if (WARN_ON(!priv->irqdomain))
> + return -ENOMEM;
While some of the stuff is cleaned up by devm, the error handling in
this code looks pretty fragile as it leaves initialized contexts,
hardware state, chained handlers etc. around.
The question is whether the system can actually boot or work at all if
any of this fails.
> +
> /*
> * We can have multiple PLIC instances so setup cpuhp state
> - * and register syscore operations only when context handler
> - * for current/boot CPU is present.
> + * and register syscore operations only after context handlers
> + * of all online CPUs are initialized.
> */
> - handler = this_cpu_ptr(&plic_handlers);
> - if (handler->present && !plic_cpuhp_setup_done) {
> + cpuhp_setup = true;
> + for_each_online_cpu(cpu) {
> + handler = per_cpu_ptr(&plic_handlers, cpu);
> + if (!handler->present) {
> + cpuhp_setup = false;
> + break;
> + }
> + }
> + if (cpuhp_setup) {
> cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
> "irqchip/sifive/plic:starting",
> plic_starting_cpu, plic_dying_cpu);
> register_syscore_ops(&plic_irq_syscore_ops);
> - plic_cpuhp_setup_done = true;
I don't think that removing the setup protection is correct.
Assume you have maxcpus=N on the kernel command line, then the above
for_each_online_cpu() loop would result in cpuhp_setup == true when the
instances for the not onlined CPUs are set up, no?
Thanks,
tglx
next prev parent reply other threads:[~2024-02-16 15:33 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-27 16:17 [PATCH v12 00/25] Linux RISC-V AIA Support Anup Patel
2024-01-27 16:17 ` [PATCH v12 01/25] irqchip/gic-v3: Make gic_irq_domain_select() robust for zero parameter count Anup Patel
2024-02-15 11:47 ` Marc Zyngier
2024-01-27 16:17 ` [PATCH v12 02/25] genirq/irqdomain: Remove the param count restriction from select() Anup Patel
2024-02-22 13:01 ` Aishwarya TCV
2024-02-22 16:28 ` Marc Zyngier
2024-02-22 22:59 ` Aishwarya TCV
[not found] ` <CGME20240223102258eucas1p119f38e40f769c883c0a502e9e26be888@eucas1p1.samsung.com>
2024-02-23 10:22 ` Marek Szyprowski
2024-02-23 10:45 ` Biju Das
2024-02-23 10:56 ` Marek Szyprowski
2024-02-23 11:01 ` Biju Das
2024-01-27 16:17 ` [PATCH v12 03/25] genirq/msi: Extend msi_parent_ops Anup Patel
2024-01-27 16:17 ` [PATCH v12 04/25] genirq/irqdomain: Add DOMAIN_BUS_DEVICE_IMS Anup Patel
2024-02-15 11:54 ` Marc Zyngier
2024-02-15 15:01 ` Thomas Gleixner
2024-01-27 16:17 ` [PATCH v12 05/25] platform-msi: Prepare for real per device domains Anup Patel
2024-01-27 16:17 ` [PATCH v12 06/25] irqchip: Convert all platform MSI users to the new API Anup Patel
2024-01-27 16:17 ` [PATCH v12 07/25] genirq/msi: Provide optional translation op Anup Patel
2024-01-27 16:17 ` [PATCH v12 08/25] genirq/msi: Split msi_domain_alloc_irq_at() Anup Patel
2024-01-27 16:17 ` [PATCH v12 09/25] genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI Anup Patel
2024-01-27 16:17 ` [PATCH v12 10/25] genirq/msi: Optionally use dev->fwnode for device domain Anup Patel
2024-01-27 16:17 ` [PATCH v12 11/25] genirq/msi: Provide allocation/free functions for "wired" MSI interrupts Anup Patel
2024-01-27 16:17 ` [PATCH v12 12/25] genirq/irqdomain: Reroute device MSI create_mapping Anup Patel
2024-01-27 16:17 ` [PATCH v12 13/25] genirq/msi: Provide MSI_FLAG_PARENT_PM_DEV Anup Patel
2024-01-27 16:17 ` [PATCH v12 14/25] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-02-16 15:33 ` Thomas Gleixner [this message]
2024-02-16 17:11 ` Anup Patel
2024-02-16 20:22 ` Thomas Gleixner
2024-02-17 5:42 ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 15/25] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2024-01-27 16:17 ` [PATCH v12 16/25] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-01-27 16:17 ` [PATCH v12 17/25] genirq/matrix: Dynamic bitmap allocation Anup Patel
2024-01-27 16:17 ` [PATCH v12 18/25] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-02-07 9:43 ` Björn Töpel
2024-02-16 18:40 ` Thomas Gleixner
2024-02-18 13:16 ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 19/25] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-02-06 15:36 ` Björn Töpel
2024-02-16 20:12 ` Thomas Gleixner
2024-02-19 4:10 ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 20/25] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-02-16 20:14 ` Thomas Gleixner
2024-02-19 4:41 ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 21/25] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-01-27 16:17 ` [PATCH v12 22/25] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2024-02-01 6:39 ` Andy Chiu
2024-02-19 10:28 ` Anup Patel
2024-02-02 9:29 ` Clément Léger
2024-02-02 10:30 ` Anup Patel
2024-02-02 10:33 ` Clément Léger
2024-02-16 20:50 ` Thomas Gleixner
2024-02-19 9:35 ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 23/25] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-02-16 21:04 ` Thomas Gleixner
2024-02-19 9:45 ` Anup Patel
2024-01-27 16:17 ` [PATCH v12 24/25] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-01-27 16:17 ` [PATCH v12 25/25] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2024-01-27 16:20 ` [PATCH v12 00/25] Linux RISC-V AIA Support Anup Patel
2024-02-14 19:54 ` Thomas Gleixner
2024-02-15 5:48 ` Anup Patel
2024-02-15 19:59 ` Thomas Gleixner
2024-02-16 21:05 ` Thomas Gleixner
2024-02-20 6:12 ` Anup Patel
2024-02-15 11:57 ` Marc Zyngier
2024-01-30 7:16 ` Björn Töpel
2024-01-30 7:52 ` Björn Töpel
2024-01-30 10:02 ` Anup Patel
2024-01-30 11:05 ` Björn Töpel
2024-01-30 10:23 ` Anup Patel
2024-01-30 11:46 ` Björn Töpel
2024-01-30 14:48 ` Björn Töpel
2024-01-30 15:19 ` Anup Patel
2024-01-30 15:48 ` Anup Patel
2024-01-30 17:49 ` Björn Töpel
2024-02-01 15:07 ` Anup Patel
2024-02-01 18:45 ` Björn Töpel
2024-02-06 15:39 ` Björn Töpel
2024-02-06 17:39 ` Anup Patel
2024-02-07 7:27 ` Björn Töpel
2024-02-07 9:18 ` Anup Patel
2024-02-07 9:37 ` Björn Töpel
2024-02-07 12:55 ` Björn Töpel
2024-02-07 13:08 ` Anup Patel
2024-02-07 13:10 ` Anup Patel
2024-02-08 10:10 ` Andrea Parri
2024-02-16 11:33 ` Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87jzn4ctks.ffs@tglx \
--to=tglx@linutronix.de \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=apatel@ventanamicro.com \
--cc=atishp@atishpatra.org \
--cc=bjorn@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=saravanak@google.com \
--cc=sunilvl@ventanamicro.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).