From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D673C6377D for ; Thu, 22 Jul 2021 10:09:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 14DCB61285 for ; Thu, 22 Jul 2021 10:09:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230410AbhGVJ2V convert rfc822-to-8bit (ORCPT ); Thu, 22 Jul 2021 05:28:21 -0400 Received: from guitar.tcltek.co.il ([192.115.133.116]:39339 "EHLO mx.tkos.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbhGVJ2U (ORCPT ); Thu, 22 Jul 2021 05:28:20 -0400 Received: from tarshish (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 5C872440E85; Thu, 22 Jul 2021 13:08:38 +0300 (IDT) References: <1173e7b0b58730fd187871d9e14a02cab85158cc.1626176145.git.baruch@tkos.co.il> <20210714201839.kfyqcyvowekc4ejs@pengutronix.de> <87eebyst5z.fsf@tarshish> <20210716070427.kv7w6imp2zoxhyz5@pengutronix.de> User-agent: mu4e 1.4.15; emacs 27.1 From: Baruch Siach To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Andy Gross , Rob Herring , Bjorn Andersson , Kathiravan T , Thierry Reding , kernel@pengutronix.de, Robert Marko , Lee Jones , linux-arm-kernel@lists.infradead.org, Balaji Prakash J Subject: Re: [PATCH v5 2/4] pwm: driver for qualcomm ipq6018 pwm block In-reply-to: <20210716070427.kv7w6imp2zoxhyz5@pengutronix.de> Date: Thu, 22 Jul 2021 13:08:47 +0300 Message-ID: <87k0lizmmo.fsf@tarshish> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Uwe, On Fri, Jul 16 2021, Uwe Kleine-König wrote: > On Fri, Jul 16, 2021 at 08:51:20AM +0300, Baruch Siach wrote: >> On Wed, Jul 14 2021, Uwe Kleine-König wrote: >> > On Tue, Jul 13, 2021 at 02:35:43PM +0300, Baruch Siach wrote: >> >> + val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | >> >> + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); >> >> + ipq_pwm_reg_write(pwm, IPQ_PWM_CFG_REG0, val); >> >> + >> >> + val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); >> >> + ipq_pwm_reg_write(pwm, IPQ_PWM_CFG_REG1, val); >> >> + >> >> + /* Enable needs a separate write to REG1 */ >> >> + val |= IPQ_PWM_REG1_UPDATE; >> > >> > Setting this bit results in the two writes above being configured >> > atomically so that no mixed settings happen to the output, right? >> >> I guess so. I have no access to hardware documentation, mind you. I >> first tried to do only one write to REG1, but it had no effect. The >> existence of the UPDATE bit also indicates that hardware works as you >> suggest. > > I wouldn't trust HW documentation here. If you have some means to > inspect the waveform this is easy to test. Depending on how long you can > make the periods an LED is enough. If you start with a slower parent > clk, a big pre_div and hi_dur = 0 the LED is supposed to be off. Then > set hi_dur = pwm_div/2 which either make the LED blink slowly or keeps > off. Then setting pre_div = 2 either increased the blink frequency or it > doesn't. ... I currently have only access to DVM to measure the PWM effect. I'll try to do more measures when I have access to better equipment. baruch -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -