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Fri, 12 Sep 2025 14:57:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1757681852; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=AKTqAHrzTqK2etFjJsAwB8b24D1cRMcQiVtfJ6wvNcQ=; b=HxtNRvlXl7AgpEYwX4jV3sGSiMtCIrbcAJTzAaXRgI3+WvwtmJsxO65WY788GJnNyEYEsw uez+I/TI+as1jTGZhed28C/VnvTrMr63d5RWvmwRcQwbs5MLhNSFmab/LAyM4bfJ7gDD4j MPCdipnIWXWqhitAMHSjYDsaVuIxOZ/UMEjD63X2yUuxoO9yRqUGon+86cJ+2lqRIPZL4b 9C1E5nf7cg0pO/qQzEr+NYNYCpg8EthAZ/eqYuiJh+gzvPIiiKVndlTyf4bUnWsDa1xTZB mjGf+MVTvdZharqWHgGztfa7cRPlMNzPjd4QFTia43/1HKImzdjhPF5oehP+cg== From: Gregory CLEMENT To: Josua Mayer , Andrew Lunn , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wunderlich Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Josua Mayer , stable@vger.kernel.org Subject: Re: [PATCH v2 2/4] arm64: dts: marvell: cn9132-clearfog: disable eMMC high-speed modes In-Reply-To: <20250911-cn913x-sr-fix-sata-v2-2-0d79319105f8@solid-run.com> References: <20250911-cn913x-sr-fix-sata-v2-0-0d79319105f8@solid-run.com> <20250911-cn913x-sr-fix-sata-v2-2-0d79319105f8@solid-run.com> Date: Fri, 12 Sep 2025 14:57:28 +0200 Message-ID: <87ldmjomkn.fsf@BLaptop.bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Josua Mayer writes: > Similar to MacchiatoBIN the high-speed modes are unstable on the CN9132 > CEX-7 module, leading to failed transactions under normal use. > > Disable all high-speed modes including UHS. > > Additionally add no-sdio and non-removable properties as appropriate for > eMMC. > > Fixes: e9ff907f4076 ("arm64: dts: add description for solidrun cn9132 cex= 7 module and clearfog board") > Cc: > Signed-off-by: Josua Mayer Applied on mvebu/fixes Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi b/arch/arm64= /boot/dts/marvell/cn9132-sr-cex7.dtsi > index afc041c1c448c3e49e1c35d817e91e75db6cfad6..bb2bb47fd77c12f1461b5b9f6= ef5567a32cc0153 100644 > --- a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi > +++ b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi > @@ -137,6 +137,14 @@ &ap_sdhci0 { > pinctrl-0 =3D <&ap_mmc0_pins>; > pinctrl-names =3D "default"; > vqmmc-supply =3D <&v_1_8>; > + /* > + * Not stable in HS modes - phy needs "more calibration", so disable > + * UHS (by preventing voltage switch), SDR104, SDR50 and DDR50 modes. > + */ > + no-1-8-v; > + no-sd; > + no-sdio; > + non-removable; > status =3D "okay"; > }; >=20=20 > > --=20 > 2.51.0 > > --=20 Gr=C3=A9gory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com