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To: Changhuang Liang <changhuang.liang@starfivetech.com>, Rob Herring
 <robh+dt@kernel.org>, Krzysztof Kozlowski
 <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>,
 Philipp Zabel <p.zabel@pengutronix.de>
Cc: Leyfoon Tan <leyfoon.tan@starfivetech.com>, Jack Zhu
 <jack.zhu@starfivetech.com>, "linux-kernel@vger.kernel.org"
 <linux-kernel@vger.kernel.org>, "devicetree@vger.kernel.org"
 <devicetree@vger.kernel.org>
Subject: Re: =?utf-8?B?5Zue5aSNOg==?= [PATCH v2 2/2] irqchip: Add StarFive
 external interrupt
 controller
In-Reply-To: <SHXPR01MB0671BD046F6E3F3A215414A6F252A@SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn>
References: <20240130055843.216342-1-changhuang.liang@starfivetech.com>
 <20240130055843.216342-3-changhuang.liang@starfivetech.com>
 <87cyt0ivn3.ffs@tglx>
 <SHXPR01MB0671BD046F6E3F3A215414A6F252A@SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn>
Date: Tue, 20 Feb 2024 10:28:02 +0100
Message-ID: <87o7cbiixp.ffs@tglx>
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On Sun, Feb 18 2024 at 02:36, Changhuang Liang wrote:
>> On Mon, Jan 29 2024 at 21:58, Changhuang Liang wrote:
> [...]
>> > +static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32
>> > +reg, u32 mask, u32 data) {
>> > +	u32 value;
>> > +
>> > +	value = ioread32(irqc->base + reg) & ~mask;
>> > +	data &= mask;
>> 
>> Why?
>> 
>
> If I want to update the reg  GENMASK(7, 4)  to value 5, the data I
> will pass in 5 << 4

All call sites pass a single bit to set/clear, right? So this GENMASK
argument does not make sense at all.

Thanks,

        tglx