From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8856C37BE8E; Fri, 15 May 2026 08:21:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778833275; cv=none; b=UGx3yM26kefbo86lbUtBg+JOE6f08GnwLh+MuDhrDCGJXvZaIAkh5OqQ4jnM4xMAblTlhp3EbL1IkZ+EmHKkuTYiosnadhsUw9KVfRfc1P9mViFIpKIs4dNf2XTsTVb82BCT0GkAbP4Q7ZrfWiwXvSuraRrKl8EtHNgumct5Ug4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778833275; c=relaxed/simple; bh=fncsyLLDmUrl81XOBce8mHfBxoufAcTXHGLJ6bqsG7E=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=KtMM8Vx912GWAgubfQgBQv2DoCb9JUWYXRfIc6y7F9A9al/333bpJ25CVAHONVzlZ5SDZdtcvQHx9fc6j6MOYnesScUGymfr64AfMascgw0N0WDoBeQ5rfbIKBQPZo2xjLypCY67A6IVIe04RayPk+zpjQTEkO7hC4nXpytXr2k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RONHB/qJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RONHB/qJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25A4AC2BCB0; Fri, 15 May 2026 08:21:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778833275; bh=fncsyLLDmUrl81XOBce8mHfBxoufAcTXHGLJ6bqsG7E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=RONHB/qJX7Ul1SwBf8w5jd1/wiJlcPuopA9ysOcyCb94v4nTqEMfiHO8PJx0v7CLU YVzE4FuZranY00gdvM9yyFsgiQt/4bWSklthqBzHevyQCwmjokoyPUzbLjV1LFpm3b 6yk6MqofiEDxiQWnB8L5hf9KWav78XnN1B07FC1tKb8aKoszt8VnIKddjKaEcDT/tv bi3IvE0HzoZB1A0CEnkYiiWHxWgcCkNLNyaRrctQgSxp9nUeHE0u9h7MxtcWxhSg3h EFby8Ja5+5Eh0OLe0+6e2KbeqElZWqMX098hy3tHhy4kEGaEda/x9tl2FX8GueMqPj o3IQVSnGw8HiQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wNnnF-00000002byC-0ORI; Fri, 15 May 2026 08:21:13 +0000 Date: Fri, 15 May 2026 09:24:28 +0100 Message-ID: <87se7t9j2b.wl-maz@kernel.org> From: Marc Zyngier To: sashiko-reviews@lists.linux.dev Cc: robh@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Subject: Re: [PATCH v2 13/17] arm64: dts: qcom: Add EL2 virtual timer interrupt In-Reply-To: <20260514230629.34892C2BCB3@smtp.kernel.org> References: <20260514150945.3917510-14-maz@kernel.org> <20260514230629.34892C2BCB3@smtp.kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sashiko-reviews@lists.linux.dev, robh@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 15 May 2026 00:06:26 +0100, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] The commit message claims to add the EL2 virtual timer interrupt, but for `sdx75.dtsi` and `milos.dtsi` it actually adds the EL2 physical timer interrupt (`GIC_PPI 10`). > -- > > commit 3f4b80b2c0c05477bcee12a9ba5b2e0a5b15a672 > Author: Marc Zyngier > > arm64: dts: qcom: Add EL2 virtual timer interrupt > > This commit adds the missing EL2 virtual timer interrupt to the timer nodes > across multiple Qualcomm SoC device trees. > > > arm64: dts: qcom: Add EL2 virtual timer interrupt > > > > The ARMv8.1+ based CPUs used in a number of Qualcomm SoCs are missing > > the EL2 virtual timer interrupt. Add it. > > Is this description entirely accurate? > > The commit message explicitly states it adds the missing EL2 virtual timer > interrupt, but it appears to also add the EL2 physical timer interrupt in > a couple of files where the virtual timer was already present. > > [ ... ] > > > diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi > > index 4a64a98a434b6..b991124b8ce9f 100644 > > --- a/arch/arm64/boot/dts/qcom/milos.dtsi > > +++ b/arch/arm64/boot/dts/qcom/milos.dtsi > > @@ -3235,6 +3235,7 @@ timer { > > interrupts = , > > , > > , > > + , > > ; > > }; > > }; > > Does this inadvertently add the EL2 physical timer instead of the virtual > timer? > > The virtual timer (GIC_PPI 12) is already present here, and this addition > is for GIC_PPI 10. > > [ ... ] > > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > > index d1b61530b562f..b6cdf71051026 100644 > > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > > @@ -1583,6 +1583,7 @@ timer { > > interrupts = , > > , > > , > > + , > > ; > > }; > > }; > > Similarly, could the commit message be updated to mention this fix, or > should this physical timer addition be split into a separate patch? These hunks were not supposed to be there, and were intended as a separate fix (though I suspect these machines have never booted Linux at EL2...). I'll drop that from the next round. M. -- Jazz isn't dead. It just smells funny.