From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CC32C433F5 for ; Mon, 18 Apr 2022 12:48:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239710AbiDRMul (ORCPT ); Mon, 18 Apr 2022 08:50:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240645AbiDRMtr (ORCPT ); Mon, 18 Apr 2022 08:49:47 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB4612C65C; Mon, 18 Apr 2022 05:34:04 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 38FE2610F4; Mon, 18 Apr 2022 12:34:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A0766C385A1; Mon, 18 Apr 2022 12:34:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650285243; bh=L5R/v4sHI6rV04SHHUZi5wOoFWpDnT4xqKF6/3cKyl4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=u9bOvlRUZMy7+ggYsfFYV/4ulLBPFYISduMjTDTx0mtTvKrvcRIwf6iz5gWfzCMD/ Px6Q+BoHmUtcnNA0N18/6gGzqvAkP4FsWBvRMBnwiCJ8/kRKDsqF3EgWNmRDK8Tior jRx1WLtN6tBQHGGnmk0rSK+hyIg9VDNluecSBtwaSWIV0Wi6AwkQzzNgU/zjJxHj+9 nCfu3t4xKSJrz3XbV/KsNCoBZkJQB+m5nW5YoZe0mJ2MWeXVRL03qXSjyo6kWq3O4K 81V92uuN6sxiVVhYe6LkBFhbD2Vph5+XJo+T4CvX7pH2EvNbxRJgfDHs67nlyALgOk hz1vwedtdYVGw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ngQZt-0050pH-7a; Mon, 18 Apr 2022 13:34:01 +0100 Date: Mon, 18 Apr 2022 13:34:00 +0100 Message-ID: <87sfqaa7uv.wl-maz@kernel.org> From: Marc Zyngier To: Peter Geis Cc: Lorenzo Pieralisi , Rob Herring , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Bjorn Helgaas , Heiko Stuebner , "open list:ARM/Rockchip SoC..." , PCI , devicetree , arm-mail-list , Linux Kernel Mailing List Subject: Re: [PATCH v7 2/4] PCI: dwc: rockchip: add legacy interrupt support In-Reply-To: References: <20220416110507.642398-1-pgwipeout@gmail.com> <20220416110507.642398-3-pgwipeout@gmail.com> <308e9c47197d4f7ae5a31cfcb5a10886@kernel.org> <87zgkk9gtc.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: pgwipeout@gmail.com, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de, linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, 18 Apr 2022 12:37:00 +0100, Peter Geis wrote: > > On Sun, Apr 17, 2022 at 5:53 AM Marc Zyngier wrote: > > > > On Sat, 16 Apr 2022 14:24:26 +0100, > > Peter Geis wrote: > > > > > > Okay, that makes sense. I'm hitting the entire block when it should be > > > the individual IRQ. > > > I also notice some drivers protect this with a spinlock while others > > > do not, how should this be handled? > > > > It obviously depends on how the HW. works. If this is a shared > > register using a RMW sequence, then you need some form of mutual > > exclusion in order to preserve the atomicity of the update. > > > > If the HW supports updating the masks using a set of hot bits (with > > separate clear/set registers), than there is no need for locking. In > > your case PCIE_CLIENT_INTR_MASK_LEGACY seems to support this odd > > "write-enable" feature which can probably be used to implement a > > lockless access, something like: > > > > void mask(struct irq_data *d) > > { > > u32 val = BIT(d->hwirq + 16) | BIT(d->hwirq); > > This is what HIWORD_UPDATE_BIT does, it's rather common in Rockchip code. > I believe I can safely drop the spinlock when enabling/disabling > individual interrupts. Yes. > > > writel_relaxed(val, ...); > > } > > > > void mask(struct irq_data *d) > > { > > u32 val = BIT(d->hwirq + 16); > > writel_relaxed(val, ...); > > } > > > > Another thing is that it is completely unclear to me what initialises > > these interrupts the first place (INTR_MASK_LEGACY, INTR_EN_LEGACY). > > Are you relying on the firmware to do that for you? > > There is no dedicated mask or enable/disable for the legacy interrupt > line (unless it's undocumented). I'm talking about the INTR_MASK_LEGACY and INTR_EN_LEGACY registers, which control the INTx (although the latter seems to default to some reserved values). I don't see where you initialise them to a state where they are enabled and masked, which should be the initial state once this driver has probed. The output interrupt itself is obviously controlled by the GIC driver. > It appears to be enabled via an "or" function with the emulated interrupts. > As far as I can tell this is common for dw-pcie, looking at the other drivers. I think we're talking past each other. I'm solely concerned with the initialisation of the input control registers, for which I see no code in this patch. M. -- Without deviation from the norm, progress is not possible.