From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32B16C43334 for ; Sun, 26 Jun 2022 12:36:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234318AbiFZMgB (ORCPT ); Sun, 26 Jun 2022 08:36:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230287AbiFZMf4 (ORCPT ); Sun, 26 Jun 2022 08:35:56 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A44C3BE18; Sun, 26 Jun 2022 05:35:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 43646B80D8B; Sun, 26 Jun 2022 12:35:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DC6E2C34114; Sun, 26 Jun 2022 12:35:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656246948; bh=kgILFkQW8EKntDsgiLCwcU/83oA2a+0SjovrqkhD+sU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Ul1UTYw/GmueCTeMSPAjhfr/LlBNrMuj7LEeD12kdHh69LpOkA+dbC7svOQiJU78Y 1FvtUrUH7PjJoauwoI8kpV4w3cjZNWg/SEiVyJpO2D/gUJlmM2KRq29kZT1sF+L+5A qogXwRMnYKkG90HCxTv61y+gpJoMfOn9W3FGsipF0a9x/DC5uZaul3V+WPIcSC3lVI cogtSN4ki31kpBFsr7bx6W3pT68Xoe1lF9hUmpgL5ou0KjadTn3PxmHz/5Av14u+gR c4DZiBvVKf3R4FZUAC7R32pcf/yStJeuWH6SjCH5ZovdDmoyTkeTGylrLGZQqMdXyn PQDE97cXasT2A== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o5RUQ-003CjU-OP; Sun, 26 Jun 2022 13:35:46 +0100 Date: Sun, 26 Jun 2022 13:35:54 +0100 Message-ID: <87tu87eh5h.wl-maz@kernel.org> From: Marc Zyngier To: Lad Prabhakar Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das Subject: Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC In-Reply-To: <20220626004326.8548-2-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220626004326.8548-2-prabhakar.mahadev-lad.rj@bp.renesas.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: prabhakar.mahadev-lad.rj@bp.renesas.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sagar.kadam@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, prabhakar.csengg@gmail.com, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sun, 26 Jun 2022 01:43:25 +0100, Lad Prabhakar wrote: > > Document Renesas RZ/Five (R9A07G043) SoC. > > Signed-off-by: Lad Prabhakar > --- > v1->v2: > * Fixed binding doc > * Fixed review comments pointed by Krzysztof. > > RFC->v1: > * Fixed Review comments pointed by Geert and Rob > --- > .../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++-- > 1 file changed, 41 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index 27092c6a86c4..59df367d1e44 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -28,7 +28,10 @@ description: > > While the PLIC supports both edge-triggered and level-triggered interrupts, > interrupt handlers are oblivious to this distinction and therefore it is not > - specified in the PLIC device-tree binding. > + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), > + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need > + to specify the interrupt type as the flow for EDGE interrupts is different > + compared to LEVEL interrupts. > > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > @@ -57,6 +60,7 @@ properties: > - enum: > - allwinner,sun20i-d1-plic > - const: thead,c900-plic > + - const: renesas,r9a07g043-plic Since it is the NCEPLIC100 that is broken, shouldn't the compatible string actually reflect that? I'd rather see 'andes,nceplic100' once and for all instead of starting with Renesas, quickly followed by all the other licensees that will inevitably integrate the same IP (which isn't even specific to the AX45MP). This IP also comes with all sort of added (mis-)features, which may or may not be used in the future, and it would make sense to identify it specifically. M. -- Without deviation from the norm, progress is not possible.