From: Felipe Balbi <balbi@kernel.org>
To: Rob Herring <robh@kernel.org>, Manish Narani <manish.narani@xilinx.com>
Cc: gregkh@linuxfoundation.org, michal.simek@xilinx.com,
p.zabel@pengutronix.de, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@xilinx.com
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller
Date: Thu, 24 Sep 2020 10:16:41 +0300 [thread overview]
Message-ID: <87wo0jejae.fsf@kernel.org> (raw)
In-Reply-To: <20200922195410.GA3122345@bogus>
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Rob Herring <robh@kernel.org> writes:
> On Thu, Sep 10, 2020 at 12:33:04AM +0530, Manish Narani wrote:
>> Add documentation for Versal DWC3 controller. Add required property
>> 'reg' for the same. Also add optional properties for snps,dwc3.
>>
>> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
>> ---
>> .../devicetree/bindings/usb/dwc3-xilinx.txt | 20 +++++++++++++++++--
>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
>> index 4aae5b2cef56..219b5780dbee 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
>> @@ -1,7 +1,8 @@
>> Xilinx SuperSpeed DWC3 USB SoC controller
>>
>> Required properties:
>> -- compatible: Should contain "xlnx,zynqmp-dwc3"
>> +- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
>> +- reg: Base address and length of the register control block
>> - clocks: A list of phandles for the clocks listed in clock-names
>> - clock-names: Should contain the following:
>> "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
>> @@ -13,12 +14,24 @@ Required child node:
>> A child node must exist to represent the core DWC3 IP block. The name of
>> the node is not important. The content of the node is defined in dwc3.txt.
>>
>> +Optional properties for snps,dwc3:
>> +- dma-coherent: Enable this flag if CCI is enabled in design. Adding this
>> + flag configures Global SoC bus Configuration Register and
>> + Xilinx USB 3.0 IP - USB coherency register to enable CCI.
>> +- snps,enable-hibernation: Add this flag to enable hibernation support for
>> + peripheral mode.
>
> This belongs in the DWC3 binding. It also implies that hibernation is
> not supported by any other DWC3 based platform. Can't this be implied by
> the compatible string (in the parent)?
hibernation support is detectable in runtime, and we've been using that.
--
balbi
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next prev parent reply other threads:[~2020-09-24 7:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 19:03 [PATCH v2 0/2] Add a separate DWC3 OF driver for Xilinx platforms Manish Narani
2020-09-09 19:03 ` [PATCH v2 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller Manish Narani
2020-09-22 19:54 ` Rob Herring
2020-09-24 7:16 ` Felipe Balbi [this message]
2020-09-25 6:07 ` Manish Narani
2020-09-25 7:11 ` Felipe Balbi
2020-09-25 7:37 ` Manish Narani
2020-09-09 19:03 ` [PATCH v2 2/2] usb: dwc3: Add driver for Xilinx platforms Manish Narani
2020-10-06 13:03 ` Manish Narani
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