From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B28DB2BCF5D for ; Mon, 9 Mar 2026 17:03:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773075819; cv=none; b=gcF0cSpGk3kDvX5/2/u8wp/wxgQmz1LMXN37cHaTjqjgxr+2tnFrgAR3BHYCOJMM58fCEW3jtr6VIgcU2SQvX4huOmfWnvMMuqSFoVL7dQEtlZHmqqx0JA5XlW6uutS1b/ugW0Ms28sW5E/OxoPVEQru4PAeMX22Q5MZmy070Es= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773075819; c=relaxed/simple; bh=fzKLGDNcL/HGtRr2uCf5lZMpMjzLVC/6hKo5DUzW7SU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=jI9YExpQZocVy8hnCqr/2v5WAekEA+z6rlnSTrWg+KIFWxpky5tJ+DNUbOi/Lvl/b326vhxMM6BMssOf9L9rIwhF4n28lSCW7CLQ7EC7gT7mOqT10I/tFTmy0/p8gMfv6lBOib13xnExTJyNapPLyANF4ERSD/TwC4x3yGuwKAI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=y3A5iDFs; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="y3A5iDFs" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id C61014E425DB; Mon, 9 Mar 2026 17:03:33 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 97EE95FFB8; Mon, 9 Mar 2026 17:03:33 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E7E6A10369820; Mon, 9 Mar 2026 18:03:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773075812; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=a0ANqTqSXTqDV3jREv3lQZk2+0Yu8cvVpizEo4IZBWA=; b=y3A5iDFs/YaYIeaCg1ipbWbVlahMGpw2BKY4n1BVS1tlJaP/pg0IldPatQgcT2sjnOASXT EDyqiJN9rYfFedAVJIpvM88wHl8GiJS5xPxm5D1eWgpGsiFwbP1cM4uccccsMTnlbfLLw2 sIhqYsM76QVQv74PM/BHsVaNSACaDG602s1BqH0penRtICX1ZP91KaKBZ7XPNyiURpM4Gm isR0FjscNI8TEhStJa2eyLEHmNBtWynZVsbdPchksgRfi0fZuN9LlkbpTssonYKc8By7Te RipidXTRFbZtUZI9Ev12sOrtgJ4vWSmOfkcqnkX4YxVWKjrCTpF9WJRz1G+ujA== From: Miquel Raynal To: Cheng Ming Lin Cc: Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tudor Ambarus , Mikhail Kshevetskiy , Pablo Martin-Gomez , Tianling Shen , Pratyush Yadav , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: Re: [PATCH v8 0/3] mtd: spi-nand: Add support for randomizer feature In-Reply-To: <20260305071042.1193522-1-linchengming884@gmail.com> (Cheng Ming Lin's message of "Thu, 5 Mar 2026 15:10:39 +0800") References: <20260305071042.1193522-1-linchengming884@gmail.com> User-Agent: mu4e 1.12.7; emacs 30.2 Date: Mon, 09 Mar 2026 18:03:23 +0100 Message-ID: <87y0k1lyuc.fsf@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Hello Cheng Ming, On 05/03/2026 at 15:10:39 +08, Cheng Ming Lin w= rote: > From: Cheng Ming Lin > > This patch series introduces randomizer support for SPI NAND devices. > > - Patch 1: add the nand-randomizer-enable and nand-randomizer-disable > boolean properties to the generic nand-chip.yaml bindings. > - Patch 2: add the initialization logic and the set_randomizer callback > to the core framework. The core will now parse the device tree > properties and enable or disable the randomizer accordingly > during spinand_init. > - Patch 3: implement the set_randomizer callback specifically for Macronix > chips (MX35LF/UF series) to handle the vendor-specific register > operations. MTD part LGTM. Let's see if the dt-binding are ok, they look fine. Thanks, Miqu=C3=A8l