[PATCH v5 00/12] Add Support for RZ/G3E ICU

[PATCH v5 00/12] Add Support for RZ/G3E ICU

[Biju Das]

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register base offset is 0x800 instead of zero.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 16 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Add support for the RZ/G3E ICU driver.

Note:
  The SoC dtsi patch is dropped from series as it is queued for
  renesas-devel.

v4->v5:
 * Collected tags from Geert.
 * Added a new patch for fixing wrong variable usage in
   rzv2h_tint_set_type().
 * Shortened tssr calculation in rzv2h_tint_irq_endisable().
 * Added tssr_shift_factor variable for optimizing the calculation
   in rzv2h_tint_set_type().
 * Dropped unnecessary parenthesis for calculating tssr in
   rzv2h_tint_set_type().
v3->v4:
 * Updated typo in commit description register offset->register
   base offset.
 * Update typo 15->16 for the number of TSSR registers in RZ/G3E
 * Collected tags.
 * Fixed the typo varable->variable.
 * Started using field_width to handle the SoC differences ad dropped the
   variables tien, tssel_mask,tssel_shift and tssr_k.
 * Dropped RZG3E_* macros from SoC dtsi.
v2->v3:
 * Added a new patch for cleanup using devm_add_action_or_reset() for
   calling put_device() in error path of rzv2h_icu_init() to simplify
   the code by using recently added devm_*helpers.
 * Replaced 'goto put_dev' by 'return xxx' as put_dev() called by
   devm_add_action_or_reset()
v1->v2:
 * Collected tags
 * Split the simplification patch into two.
 * Updated commit header and description for patch#4.
 * Replaced devm_reset_control_get_optional_exclusive_deasserted()->
   devm_reset_control_get_exclusive_deasserted().
 * Moved simplification using devm_pm_runtime_enable() to patch#5.
 * Aligned kernel doc, struct members and struct initializers in
   a tabular fashion.
 * Renamed the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL.
 * Replaced hexa decimal constant with ICU_RZV2H_TSSEL_MAX_VAL in struct
   rzv2h_hw_params.
 * Introduced ICU_RZG3E_{TSSEL_MAX_VAL,TINT_OFFSET} macros and used these
   macros in struct rzv2h_hw_params rather than using the hex constants.

Biju Das (12):
  dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
    SoC
  irqchip/renesas-rzv2h: Fix wrong variable usage in
    rzv2h_tint_set_type()
  irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
  irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
  irqchip/renesas-rzv2h: Use
    devm_reset_control_get_exclusive_deasserted()
  irqchip/renesas-rzv2h: Use devm_pm_runtime_enable()
  irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
  irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add field_width variable to struct
    rzv2h_hw_info
  irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
  irqchip/renesas-rzv2h: Drop macros ICU_TSSR_TSSEL_{MASK,PREP}
  irqchip/renesas-rzv2h: Add RZ/G3E support

 .../renesas,rzv2h-icu.yaml                    |   6 +-
 drivers/irqchip/irq-renesas-rzv2h.c           | 189 ++++++++++++------
 2 files changed, 133 insertions(+), 62 deletions(-)

-- 
2.43.0

[PATCH v5 01/12] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC

[Biju Das]

Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
SoC is almost identical to the one found on the RZ/V2H SoC, with the
following differences:
 - The TINT register base offset is 0x800 instead of zero.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 16 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E
SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * No change.
v3->v4:
 * Updated typo in commit description offset->base offset.
 * Update typo 15->16 for the number of TSSR registers in RZ/G3E
 * Collected tags.
v2->v3:
 * No change.
v1->v2:
 * Collected tags.
---
 .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml    | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
index d7ef4f1323a7..3f99c8645767 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/V2H(P) Interrupt Control Unit
+title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit
 
 maintainers:
   - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
@@ -20,7 +20,9 @@ description:
 
 properties:
   compatible:
-    const: renesas,r9a09g057-icu # RZ/V2H(P)
+    enum:
+      - renesas,r9a09g047-icu # RZ/G3E
+      - renesas,r9a09g057-icu # RZ/V2H(P)
 
   '#interrupt-cells':
     description: The first cell is the SPI number of the NMI or the
-- 
2.43.0

RE: [PATCH v5 00/12] Add Support for RZ/G3E ICU

[Biju Das]

Hi Thomas,

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 12 February 2025 11:12
> Subject: [PATCH v5 00/12] Add Support for RZ/G3E ICU
> 
> The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the
> following differences:
>  - The TINT register base offset is 0x800 instead of zero.
>  - The number of supported GPIO interrupts for TINT selection is 141
>    instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 16 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
> 
> Add support for the RZ/G3E ICU driver.
> 
> Note:
>   The SoC dtsi patch is dropped from series as it is queued for
>   renesas-devel.
> 
> v4->v5:
>  * Collected tags from Geert.
>  * Added a new patch for fixing wrong variable usage in
>    rzv2h_tint_set_type().
>  * Shortened tssr calculation in rzv2h_tint_irq_endisable().
>  * Added tssr_shift_factor variable for optimizing the calculation
>    in rzv2h_tint_set_type().
>  * Dropped unnecessary parenthesis for calculating tssr in
>    rzv2h_tint_set_type().
> v3->v4:
>  * Updated typo in commit description register offset->register
>    base offset.
>  * Update typo 15->16 for the number of TSSR registers in RZ/G3E
>  * Collected tags.
>  * Fixed the typo varable->variable.
>  * Started using field_width to handle the SoC differences ad dropped the
>    variables tien, tssel_mask,tssel_shift and tssr_k.
>  * Dropped RZG3E_* macros from SoC dtsi.
> v2->v3:
>  * Added a new patch for cleanup using devm_add_action_or_reset() for
>    calling put_device() in error path of rzv2h_icu_init() to simplify
>    the code by using recently added devm_*helpers.
>  * Replaced 'goto put_dev' by 'return xxx' as put_dev() called by
>    devm_add_action_or_reset()
> v1->v2:
>  * Collected tags
>  * Split the simplification patch into two.
>  * Updated commit header and description for patch#4.
>  * Replaced devm_reset_control_get_optional_exclusive_deasserted()->
>    devm_reset_control_get_exclusive_deasserted().
>  * Moved simplification using devm_pm_runtime_enable() to patch#5.
>  * Aligned kernel doc, struct members and struct initializers in
>    a tabular fashion.
>  * Renamed the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL.
>  * Replaced hexa decimal constant with ICU_RZV2H_TSSEL_MAX_VAL in struct
>    rzv2h_hw_params.
>  * Introduced ICU_RZG3E_{TSSEL_MAX_VAL,TINT_OFFSET} macros and used these
>    macros in struct rzv2h_hw_params rather than using the hex constants.
> 
> Biju Das (12):
>   dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
>     SoC
>   irqchip/renesas-rzv2h: Fix wrong variable usage in
>     rzv2h_tint_set_type()
>   irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
>   irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
>   irqchip/renesas-rzv2h: Use
>     devm_reset_control_get_exclusive_deasserted()
>   irqchip/renesas-rzv2h: Use devm_pm_runtime_enable()
>   irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
>   irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
>   irqchip/renesas-rzv2h: Add field_width variable to struct
>     rzv2h_hw_info
>   irqchip/renesas-rzv2h: Drop TSSR_TIEN macro
>   irqchip/renesas-rzv2h: Drop macros ICU_TSSR_TSSEL_{MASK,PREP}
>   irqchip/renesas-rzv2h: Add RZ/G3E support
> 
>  .../renesas,rzv2h-icu.yaml                    |   6 +-
>  drivers/irqchip/irq-renesas-rzv2h.c           | 189 ++++++++++++------
>  2 files changed, 133 insertions(+), 62 deletions(-)
> 

Gentle ping. Should I rebase to [1] and resend.
Please let me know.

[1] https://lore.kernel.org/all/20250220150110.738619-5-fabrizio.castro.jz@renesas.com/

Cheers,
Biju

RE: [PATCH v5 00/12] Add Support for RZ/G3E ICU

[Thomas Gleixner]

On Mon, Feb 24 2025 at 10:48, Biju Das wrote:
> Gentle ping. Should I rebase to [1] and resend.
> Please let me know.
>
> [1] https://lore.kernel.org/all/20250220150110.738619-5-fabrizio.castro.jz@renesas.com/

Yes. I've marked this series obsolete due to the discussion about patch
10.

Please rebase on top of tip irq/drivers.

Thanks,

        tglx

RE: [PATCH v5 00/12] Add Support for RZ/G3E ICU

[Biju Das]

Hi Thomas,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@linutronix.de>
> Sent: 24 February 2025 11:22
> Subject: RE: [PATCH v5 00/12] Add Support for RZ/G3E ICU
> 
> On Mon, Feb 24 2025 at 10:48, Biju Das wrote:
> > Gentle ping. Should I rebase to [1] and resend.
> > Please let me know.
> >
> > [1]
> > https://lore.kernel.org/all/20250220150110.738619-5-fabrizio.castro.jz
> > @renesas.com/
> 
> Yes. I've marked this series obsolete due to the discussion about patch 10.
> 
> Please rebase on top of tip irq/drivers.

OK, will send next version retaining the macros by adding field_width
parameter to it.

Cheers,
Biju