From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AC9FC433E3 for ; Sat, 25 Jul 2020 14:13:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CFD60206F6 for ; Sat, 25 Jul 2020 14:13:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595686380; bh=+dGVKP/thoqFXdnlsJQGDIVIpZJR0SFIbl5+nzHxG6M=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=ePv69vHBVmORQHJGHH+9QAUz+dmfBlNyiroTR8axkhHhAZ+NIouxRb2TesuIGWJ1y ClJ/cJMUS3KcQ2a/v30dVQzGzmabPaXZpMB9A8xXwd2Gcws/JNBPWEoTd3Qiy7JBuz +US7l0slZ9S92g07+t/Wp28h9/mIWan/o4jpHiD4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726904AbgGYONA (ORCPT ); Sat, 25 Jul 2020 10:13:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:39416 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726652AbgGYONA (ORCPT ); Sat, 25 Jul 2020 10:13:00 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8A3AB206D7; Sat, 25 Jul 2020 14:12:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595686379; bh=+dGVKP/thoqFXdnlsJQGDIVIpZJR0SFIbl5+nzHxG6M=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=SPTj7gGEtR4ptyH3vlg9u1aTuOsWwRMe67tllMubtdEUqAbU/vBjNt2FCxGrT1xKY c40WVM839nIRTX547JH4NKOjlj/wv5Ku82tEzJmbNsccxo4NXTUFhIqKQY4E5TCBVc KCo9D3o2HLHcyqcGt2za99boekYW47pEa8kk2ono= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jzKv4-00Er0D-3B; Sat, 25 Jul 2020 15:12:58 +0100 Date: Sat, 25 Jul 2020 15:12:57 +0100 Message-ID: <87y2n7wumu.wl-maz@kernel.org> From: Marc Zyngier To: Lokesh Vutla Cc: Rob Herring , Thomas Gleixner , Nishanth Menon , Tero Kristo , Santosh Shilimkar , Linux ARM Mailing List , Sekhar Nori , Grygorii Strashko , Peter Ujfalusi , Device Tree Mailing List , Suman Anna Subject: Re: [PATCH v3 0/9] irqchip: ti, sci-intr/inta: Update the dt bindings to accept different interrupt parents In-Reply-To: <20200724141837.4542-1-lokeshvutla@ti.com> References: <20200724141837.4542-1-lokeshvutla@ti.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26.3 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: lokeshvutla@ti.com, robh+dt@kernel.org, tglx@linutronix.de, nm@ti.com, t-kristo@ti.com, ssantosh@kernel.org, linux-arm-kernel@lists.infradead.org, nsekhar@ti.com, grygorii.strashko@ti.com, peter.ujfalusi@ti.com, devicetree@vger.kernel.org, s-anna@ti.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, 24 Jul 2020 15:18:28 +0100, Lokesh Vutla wrote: > > Hi Marc, > This is continuation of the RFC patches[0] regarding the driver > updates to support for following interrupt parent connection: > - INTR -> INTR > - INTA -> GICv3 > The current existing driver assumes that INTR is always connected to > GICv3 and INTA is always connected to INTR. > > As discussed this change breaks the DT backward compatibility but it > allows to not depend on TISCI firmware properties in DT node. IMHO, this > will ensure that any future changes will not effect DT properties. > > This series depends on the the new Yaml bindings for common TISCI[1] Assuming you fix the issues I have pointed out for patches 6 and 9, this will need some Acks for the firmware parts, as the irqchip patches are not standalone. Thanks, M. -- Without deviation from the norm, progress is not possible.