From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hiroshi Doyu Subject: Re: [PATCH v5] devicetree: Add generic IOMMU device tree bindings Date: Thu, 14 Aug 2014 19:04:52 +0300 Message-ID: <87y4ur2h23.fsf@nvidia.com> References: <1406803383-11601-1-git-send-email-thierry.reding@gmail.com> <87a9774lf5.fsf@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Varun Sethi Cc: Mark Rutland , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Stephen Warren , Arnd Bergmann , Will Deacon , Rob Herring , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , Thierry Reding , Olof Johansson , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: devicetree@vger.kernel.org Hi Varun, Varun Sethi writes: >> -----Original Message----- >> From: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org [mailto:iommu- >> bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org] On Behalf Of Hiroshi Doyu >> Sent: Thursday, August 14, 2014 12:18 PM >> To: Thierry Reding; Stephen Warren; Arnd Bergmann; Will Deacon >> Cc: Mark Rutland; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Olof Johansson; >> iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org; Rob Herring; linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; >> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org >> Subject: Re: [PATCH v5] devicetree: Add generic IOMMU device tree bindings >> >> >> Thierry Reding writes: >> >> > +Multiple-master IOMMU: >> > +---------------------- >> > + >> > + iommu { >> > + /* the specifier represents the ID of the master */ >> > + #iommu-cells = <1>; >> > + }; >> > + >> > + master@1 { >> > + /* device has master ID 42 in the IOMMU */ >> > + iommus = <&{/iommu} 42>; >> > + }; >> > + >> > + master@2 { >> > + /* device has master IDs 23 and 24 in the IOMMU */ >> > + iommus = <&{/iommu} 23>, <&{/iommu} 24>; >> > + }; >> >> I think that this "master ID" will be parsed in IOMMU driver. For example, >> ARM,SMMU expects "streamID" as "master ID", right? >> >> If a SoC has a feature to configure to assign streamID to devices at runtime, >> "streamID" is not equal to "master ID". >> >> iommus = <&{/smmu} "soc specific master ID">; >> >> "soc master ID" needs to be translated into "streamID" by SoC SW. It seems >> that ARM,SMMU kernel driver doesn't expect this kind of ID translation. If >> ARM,SMMU kernel driver is used as is, "soc master ID" >> would be incompatible? ARM,SMMU needs such translation before parsing. Is >> this my understanding right? >> >> If so I think that this master ID configuration/translation may be quite >> reasonable requirment for SoC using ARM,SMMU. >> >> Can we consider this ID translation within ARM,SMMU compatibility? >> >> IOW, is it possible to implement some SoC specific hook for ID >> translation/configuration in ARM,SMMU kernel driver? > > > Can the id translation be done using a SMR mask? No, "SoC master ID" is completely independenf of SMR. > Also, for dynamic stream ID allocation we would need to represent the > specific master register (to store the stream ID) in the device tree. I assmue that the above means that iMX has such configuration register to map steramID and a device dynamically.