From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Hrushikesh Salunke <h-salunke@ti.com>
Cc: <nm@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<s-vadapalli@ti.com>, <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<danishanwar@ti.com>
Subject: Re: [PATCH v2] arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"
Date: Tue, 10 Jun 2025 11:21:03 +0530 [thread overview]
Message-ID: <88554900-b280-425f-b79d-d065b10290a5@ti.com> (raw)
In-Reply-To: <20250610054920.2395509-1-h-salunke@ti.com>
On Tue, Jun 10, 2025 at 11:19:20AM +0530, Hrushikesh Salunke wrote:
> AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot
> on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be
> functional at all stages of PCIe boot process. Thus add the
> "bootph-all" boot phase tag to "pcie0_ep" device tree node.
>
> Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Regards,
Siddharth.
next prev parent reply other threads:[~2025-06-10 5:51 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-10 5:49 [PATCH v2] arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep" Hrushikesh Salunke
2025-06-10 5:51 ` Siddharth Vadapalli [this message]
2025-06-11 8:44 ` Vignesh Raghavendra
2025-06-11 8:47 ` Hrushikesh Salunke
2025-06-12 10:16 ` Hrushikesh Salunke
2025-06-19 7:55 ` Vignesh Raghavendra
2025-06-19 8:33 ` Hrushikesh Salunke
2025-06-26 4:03 ` Vignesh Raghavendra
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