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Thu, 08 Feb 2024 10:28:19 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 418ASICa005723 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Feb 2024 10:28:18 GMT Received: from [10.131.33.37] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 8 Feb 2024 02:28:13 -0800 Message-ID: <8865b33b-8dd6-73bf-1d34-919c6bcff65c@quicinc.com> Date: Thu, 8 Feb 2024 15:58:10 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [RFC 1/7] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings Content-Language: en-US To: Rob Herring CC: , , , , , , , , , , , References: <20240117173458.2312669-1-quic_sibis@quicinc.com> <20240117173458.2312669-2-quic_sibis@quicinc.com> <20240130171240.GA1929440-robh@kernel.org> From: Sibi Sankar In-Reply-To: <20240130171240.GA1929440-robh@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5K9c9CHb6iX1dl5E6IlpWatLuFKLv803 X-Proofpoint-ORIG-GUID: 5K9c9CHb6iX1dl5E6IlpWatLuFKLv803 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-08_01,2024-02-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 phishscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 mlxlogscore=857 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402080054 On 1/30/24 22:42, Rob Herring wrote: > On Wed, Jan 17, 2024 at 11:04:52PM +0530, Sibi Sankar wrote: >> Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox >> controller. Hey Rob, Thanks for taking time to review the series. >> >> Signed-off-by: Sibi Sankar >> --- >> .../bindings/mailbox/qcom,cpucp-mbox.yaml | 51 +++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> >> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> new file mode 100644 >> index 000000000000..2617e5555acb >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml >> @@ -0,0 +1,51 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller >> + >> +maintainers: >> + - Sibi Sankar >> + >> +description: >> + The CPUSS Control Processor (CPUCP) mailbox controller enables communication >> + between AP and CPUCP by acting as a doorbell between them. >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - qcom,x1e80100-cpucp-mbox >> + - const: qcom,cpucp-mbox > > A generic fallback implies multiple devices use the same unchanged > block. That seems doubtful given you have not defined any others and > given Konrad's comments. This mbox is expected to be used as is on a number of future SoCs, that's the only reason I added the generic fallback. I can drop it in the next re-spin if you want. -Sibi > > Rob