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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Macpaul Lin <macpaul.lin@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Yong Wu <yong.wu@mediatek.com>, Joerg Roedel <joro@8bytes.org>,
	Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	CK Hu <ck.hu@mediatek.com>, Jitao shi <jitao.shi@mediatek.com>,
	Tinghan Shen <tinghan.shen@mediatek.com>,
	Seiya Wang <seiya.wang@mediatek.com>,
	Ben Lok <ben.lok@mediatek.com>,
	"Nancy . Lin" <nancy.lin@mediatek.com>,
	dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org,
	Alexandre Mergnat <amergnat@baylibre.com>
Cc: Bear Wang <bear.wang@mediatek.com>,
	Pablo Sun <pablo.sun@mediatek.com>,
	Macpaul Lin <macpaul@gmail.com>, Sen Chu <sen.chu@mediatek.com>,
	Chris-qj chen <chris-qj.chen@mediatek.com>,
	MediaTek Chromebook Upstream
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Chen-Yu Tsai <wenst@chromium.org>
Subject: Re: [PATCH v2 2/5] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs
Date: Mon, 30 Sep 2024 10:49:06 +0200	[thread overview]
Message-ID: <8883c84d-8333-4b04-83b5-022be5b6153c@collabora.com> (raw)
In-Reply-To: <20240926111449.9245-2-macpaul.lin@mediatek.com>

Il 26/09/24 13:14, Macpaul Lin ha scritto:
> The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due
> to an excessively long 'interrupts' property. The error message was:
> 
>    infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0],
>                       [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]]
>                       is too long
> 
> To address this issue, add "minItems: 1" and "maxItems: 5" constraints to
> the 'interrupts' property in the DT binding schema. This change allows for
> flexibility in the number of interrupts for new SoCs.
> The purpose of these 5 interrupts is also added.
> 
> Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema")
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> ---
>   .../bindings/iommu/mediatek,iommu.yaml        | 25 ++++++++++++++++++-
>   1 file changed, 24 insertions(+), 1 deletion(-)
> 
> Changes for v2:
>   - commit message: re-formatting and add a description of adding 5 interrupts.
>   - add 'description' and 'maxItems: 5' for 'interrupt' property of
>     'mt8195-iommu-infra'
>   - others keeps 'maxItems: 1'
> 
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index ea6b0f5f24de..fdd2996d2a31 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -96,7 +96,8 @@ properties:
>       maxItems: 1
>   
>     interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 5
>   
>     clocks:
>       items:
> @@ -210,6 +211,28 @@ allOf:
>         required:
>           - mediatek,larbs
>   
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - mediatek,mt8195-iommu-infra
> +
> +    then:
> +      properties:
> +        interrupts:
> +          description: |

Do you really need to keep the formatting?

If you rephrase that as:

The infra IOMMU in MT8195 has five banks: each features one set
of APB registers for the normal world (set 0), one for the protected
world (sets 1-3) and one for the secure world (set 4), and each set
has its own interrupt. Therefore, five interrupts are needed.

...you won't need the bar :-)

> +            The IOMMU of MT8195 has 5 banks: 0/1/2/3/4.
> +            Each bank has a set of APB registers corresponding to the
> +            normal world, protected world 1/2/3, and secure world, respectively.
> +            Therefore, 5 interrupt numbers are needed.
> +          maxItems: 5

minItems: 5

Cheers,
Angelo



  parent reply	other threads:[~2024-09-30  8:49 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-26 11:14 [PATCH v2 1/5] arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao node Macpaul Lin
2024-09-26 11:14 ` [PATCH v2 2/5] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs Macpaul Lin
2024-09-26 16:02   ` Conor Dooley
2024-09-30  8:49   ` AngeloGioacchino Del Regno [this message]
2024-10-02  5:01     ` Macpaul Lin
2024-10-02 10:12       ` AngeloGioacchino Del Regno
2024-09-26 11:14 ` [PATCH v2 3/5] arm64: dts: mediatek: mt8395-genio-1200-evk: Fix dtbs_check error for phy Macpaul Lin
2024-09-26 11:14 ` [PATCH v2 4/5] arm64: dts: mt8195: Fix dtbs_check error for mutex node Macpaul Lin
2024-09-26 11:14 ` [PATCH v2 5/5] dt-bindings: display: mediatek: dpi: Add mt8195 support in power domains Macpaul Lin
2024-09-26 15:59   ` Conor Dooley
2024-09-27  7:02     ` Macpaul Lin

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