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Wed, 12 Aug 2026 02:21:58 -0700 (PDT) X-Received: by 2002:a05:6a20:d709:b0:3bf:e761:6285 with SMTP id adf61e73a8af0-3cc3f7433ecmr4293871637.29.1786526518355; Wed, 12 Aug 2026 02:21:58 -0700 (PDT) Received: from [10.217.217.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cbee7d52d4dsm387903a12.31.2026.08.12.02.21.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Aug 2026 02:21:58 -0700 (PDT) Message-ID: <88e4737a-a791-46d4-af33-d9de57e6d835@oss.qualcomm.com> Date: Wed, 12 Aug 2026 14:51:48 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/7] iio: adc: qcom-spmi-adc5-gen3: Add support for QCOM PMIC5 Gen4 ADC To: Andy Shevchenko Cc: Jonathan Cameron , David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Konrad Dybcio , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , Anjelique Melendez , Manaf Meethalavalappu Pallikunhi , Priyansh Jain References: <20260731-pmic5_gen4_adc-v1-0-9c49b2eea6f9@oss.qualcomm.com> <20260731-pmic5_gen4_adc-v1-2-9c49b2eea6f9@oss.qualcomm.com> Content-Language: en-US From: Jishnu Prakash In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwODEyMDA3NCBTYWx0ZWRfX9OlxHMq+5stl tVo9mayhXerOaCewCNcXgl4ORWnzgQxkV+VPbtrYD2Q8F2V8U6EKFFqXU6VpO9CR4csCRAx27GN eWduKJDAhGMvpj0JeiuAuIEgTQn04Cc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEyMDA3NCBTYWx0ZWRfX8tQo9i80dg9Q +4Iw7snwO5JN1KEMzc5efvjuwCIw8KBWToT37niemJbziapzXC0BuECpOfhdzd9XnjaCutYCXqC GVdmoaXtBPD3jk27ZnmZuAtjpGml6Pcx1rzbO/wwIlI+kmXk7rIhhsS4a6VwsgFLJEVkAS6EWkt hJgQ+/8Lh1ddYXJUUkCYEl/3K07/og0PxE7w8hW2mLiPnwckt+Vc+krg9IAGBMuyWNj3FW8gDJB JamZy16RKK2hNNfTgiy95aPm2VS15SDd2ppKNR7b32mA/aL/NSDU1kx4Q6p3hArSynCspFhwrxq uAY3VPqUgQLc9X3IL8OoE20vIC/uOWMC3VJTGkG90+PyP8YcV50g1nEArcgjEtlN4muJjJ02dKI 7FMPjr5OxnCJ+TLfo5QwimAkJN6IFXqR1icIIRYHdXzY0LOiH2PLRWT0lKp/aNz7DeQkGmJcPKA 2SpzzvmX/xqaChRYX5Q== X-Proofpoint-ORIG-GUID: zPir--LNlVfDRgBCmUHrCpInuAbs-t-6 X-Authority-Analysis: v=2.4 cv=POA/P/qC c=1 sm=1 tr=0 ts=6a7c3b37 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=TjZioY23ztXOLIvkaGkA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: zPir--LNlVfDRgBCmUHrCpInuAbs-t-6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-12_02,2026-08-10_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608120074 Hi Andy, On 8/9/2026 2:36 AM, Andy Shevchenko wrote: > On Fri, Jul 31, 2026 at 11:36:15PM +0530, Jishnu Prakash wrote: >> PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made >> for improved performance, mostly at the hardware level. >> >> One significant software change is that ratiometric conversion resolution >> has been increased from 14 bits to 16 bits, so the maximum value of >> these measurements needs to be updated for Gen4. Add a new scaling >> function for thermistor channels which use this type of conversion. >> >> In the latest PMIC arbiter version (v8), there can be up to 4 buses >> under the PMIC arbiter and 32 PMICs under each bus. In order to >> support communication between ADC on the master PMIC and ADCs on any >> of the other PMICs, a field of width 2 bits is added for bus index >> and the bits for SID are extended from 4 to 5 bits, in the SID >> register. Add support for this. >> >> In addition, it is possible that the master PMIC has ADC of one generation >> and it needs to communicate with another PMIC with ADC of a different >> generation. Add new DT properties "qcom,adc5-gen3" and "qcom,adc5-gen4", >> to distinguish Gen3 channels under a Gen4 master and Gen4 channels >> under a Gen3 master respectively, to ensure that their conversions are handled >> correctly. > > ... > >> +static const struct adc5_channels adc5_gen4_chans_pmic[ADC5_MAX_CHANNEL] = { >> + [ADC5_GEN4_OFFSET_REF] = ADC5_CHAN_VOLT(0, >> + SCALE_HW_CALIB_DEFAULT) > > Always nice to see a macro with the embedded comma... > >> + [ADC5_GEN4_1P25VREF] = ADC5_CHAN_VOLT(0, >> + SCALE_HW_CALIB_DEFAULT) >> + [ADC5_GEN4_VPH_PWR] = ADC5_CHAN_VOLT(1, >> + SCALE_HW_CALIB_DEFAULT) >> + [ADC5_GEN4_VBAT_SNS_QBG] = ADC5_CHAN_VOLT(1, >> + SCALE_HW_CALIB_DEFAULT) >> + [ADC5_GEN4_DIE_TEMP] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_PMIC_THERM_PM7) >> + [ADC5_GEN4_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> + [ADC5_GEN4_AMUX5_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, >> + SCALE_HW_CALIB_THERM_100K_PU_GEN4) >> +}; > > ... > >> enum adc5_cal_method { >> ADC5_NO_CAL = 0, > > (here as well, see below) > >> ADC5_RATIOMETRIC_CAL, > >> }; >> >> +enum adc_generation { >> + ADC5_GEN3 = 0, > > Why is this assignment? What's wrong with the C standard? > >> + ADC5_GEN4, > > If these are related to HW communication protocol or bit fields, all of them > must be explicitly assigned (to make code robust against changes in the middle > of enum). I see that ADC5_RATIOMETRIC_CAL is used for bit fields, but ADC5_GEN3/ADC5_GEN4 are not used in HW. I'll add a fix patch to explicitly assign all the enum values directly used in HW and drop the assignment for ADC5_GEN3 from this patch. Thanks, Jishnu > >> +}; >