From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: Re: [PATCH v3 2/4] clk: at91: sckc: add support to specify registers bit offsets Date: Mon, 20 May 2019 08:54:24 +0000 Message-ID: <8900ba46-7166-2b5e-961b-3786121c845f@microchip.com> References: <1557487388-32098-1-git-send-email-claudiu.beznea@microchip.com> <1557487388-32098-3-git-send-email-claudiu.beznea@microchip.com> <20190510213242.GE7622@piout.net> <20190517211336.GB7685@piout.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190517211336.GB7685@piout.net> Content-Language: en-US Content-ID: <17043DB5617E724DA7B445DF92546F4F@namprd11.prod.outlook.com> Sender: linux-kernel-owner@vger.kernel.org To: alexandre.belloni@bootlin.com Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, Nicolas.Ferre@microchip.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org DQoNCk9uIDE4LjA1LjIwMTkgMDA6MTMsIEFsZXhhbmRyZSBCZWxsb25pIHdyb3RlOg0KPiBFeHRl cm5hbCBFLU1haWwNCj4gDQo+IA0KPiBPbiAxNi8wNS8yMDE5IDA4OjEwOjM0KzAwMDAsIENsYXVk aXUuQmV6bmVhQG1pY3JvY2hpcC5jb20gd3JvdGU6DQo+Pj4+IEBAIC02OSwxMCArODAsMTEgQEAg c3RhdGljIGludCBjbGtfc2xvd19vc2NfcHJlcGFyZShzdHJ1Y3QgY2xrX2h3ICpodykNCj4+Pj4g IAl2b2lkIF9faW9tZW0gKnNja2NyID0gb3NjLT5zY2tjcjsNCj4+Pj4gIAl1MzIgdG1wID0gcmVh ZGwoc2NrY3IpOw0KPj4+PiAgDQo+Pj4+IC0JaWYgKHRtcCAmIChBVDkxX1NDS0NfT1NDMzJCWVAg fCBBVDkxX1NDS0NfT1NDMzJFTikpDQo+Pj4+ICsJaWYgKHRtcCAmIChBVDkxX1NDS0NfT1NDMzJC WVAob3NjLT5iaXRzKSB8DQo+Pj4+ICsJCSAgIEFUOTFfU0NLQ19PU0MzMkVOKG9zYy0+Yml0cykp KQ0KPj4+DQo+Pj4gSSBzdGlsbCBmaW5kIHRoYXQ6DQo+Pj4NCj4+PiAJaWYgKHRtcCAmIChvc2Mt PmJpdHMtPmNyX29zYzMyYnlwIHwgb3NjLT5iaXRzLT5jcl9vc2MzMmVuKSkNCj4+Pg0KPj4+IHdv dWxkIGJlIHNob3J0ZXIgYW5kIGVhc2llciB0byByZWFkIGFuZCBzdGlsbCBmaXRzIG9uIG9uZSBs aW5lLg0KPj4NCj4+IEFncmVlLCBidXQgSSB0aG91Z2h0IHRvIHVzZSB0aGUgc2FtZSBpbnRlcmZh Y2UgZXZlcnl3aGVyZS4gQW55d2F5LCB0ZWxsIG1lDQo+PiBpZiB5b3Ugd2FudCB0byByZXNlbmQg d2l0aCB0aGVzZSBjaGFuZ2VzLg0KPj4NCj4gTXkgY29tbWVudCBhcHBsaWVzIHRvIGFsbCB0aGUg QVQ5MV9TQ0tDXy4qKCkgbWFjcm9zLiBJIGRvbid0IGZlZWwgdGhhdA0KPiB0aGUgbWFjcm9zIG1h a2UgdGhlIGNvZGUgY2xlYXJlciwgYWNjZXNzaW5nIGJpdHMtPmNyXy4qIGlzIHNlbGYNCj4gZG9j dW1lbnRpbmcgZW5vdWdoIChhbmQgbWFrZXMgdGhlIGNvZGUgc2hvcnRlcikuDQoNCk9LLCBJJ2xs IHNlbmQgYSBuZXcgdmVyc2lvbiB0YWtpbmcgdGhpcyBpbnRvIGNvbnNpZGVyYXRpb24uDQoNCj4g DQo=