[PATCH v2 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc

[PATCH v2 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc

[Michal Simek]

All Xilinx boards can hosts also soft core CPUs like MicroBlaze or
MicroBlaze V (RISC-V ISA) that's why move boar description from arm folder
to soc folder.
Similar chagne was done for Renesas by commit c27ce08b806d ("dt-bindings:
soc: renesas: Move renesas.yaml from arm to soc").

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

Changes in v2:
- New patch in the series

Based on discussion here.
https://lore.kernel.org/r/20231108-copper-scoff-b4de5febb954@spud

---
 .../devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml          | 0
 MAINTAINERS                                                      | 1 +
 2 files changed, 1 insertion(+)
 rename Documentation/devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml (100%)

diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
similarity index 100%
rename from Documentation/devicetree/bindings/arm/xilinx.yaml
rename to Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
diff --git a/MAINTAINERS b/MAINTAINERS
index ea790149af79..14ad00009a63 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3020,6 +3020,7 @@ F:	Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
 F:	Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
 F:	Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
 F:	Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
+F:	Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
 F:	Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
 F:	arch/arm/mach-zynq/
 F:	drivers/clocksource/timer-cadence-ttc.c
-- 
2.36.1

[PATCH v2 2/2] dt-bindings: soc: Add new board description for MicroBlaze V

[Michal Simek]

MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor. Processor can
be used with standard AMD/Xilinx IPs including interrupt controller and
timer.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

Changes in v2:
- Put MicroBlaze V description to xilinx.yaml
- Add qemu target platform as platform used for testing.

 Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index f57ed0347894..ec8155a343d0 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -132,6 +132,11 @@ properties:
           - const: xlnx,zynqmp-smk-k26
           - const: xlnx,zynqmp
 
+      - description: AMD MicroBlaze V (QEMU)
+        items:
+         - const: qemu,mbv
+         - const: amd,mbv
+
 additionalProperties: true
 
 ...
-- 
2.36.1

Re: [PATCH v2 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc

[Krzysztof Kozlowski]

On 22/11/2023 10:13, Michal Simek wrote:
> All Xilinx boards can hosts also soft core CPUs like MicroBlaze or
> MicroBlaze V (RISC-V ISA) that's why move boar description from arm folder

Boards are cute, but boars are cutter :)

s/boar/boards/

> to soc folder.
> Similar chagne was done for Renesas by commit c27ce08b806d ("dt-bindings:
> soc: renesas: Move renesas.yaml from arm to soc").

The reason for Renesas was that otherwise same compatible would be in
two places: arm and riscv schema.

Are you going to have the same case?


Best regards,
Krzysztof

Re: [PATCH v2 2/2] dt-bindings: soc: Add new board description for MicroBlaze V

[Krzysztof Kozlowski]

On 22/11/2023 10:13, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor. Processor can
> be used with standard AMD/Xilinx IPs including interrupt controller and
> timer.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
> Changes in v2:
> - Put MicroBlaze V description to xilinx.yaml
> - Add qemu target platform as platform used for testing.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc

[Michal Simek]

On 11/22/23 11:06, Krzysztof Kozlowski wrote:
> On 22/11/2023 10:13, Michal Simek wrote:
>> All Xilinx boards can hosts also soft core CPUs like MicroBlaze or
>> MicroBlaze V (RISC-V ISA) that's why move boar description from arm folder
> 
> Boards are cute, but boars are cutter :)
> 
> s/boar/boards/

:-)

> 
>> to soc folder.
>> Similar chagne was done for Renesas by commit c27ce08b806d ("dt-bindings:
>> soc: renesas: Move renesas.yaml from arm to soc").
> 
> The reason for Renesas was that otherwise same compatible would be in
> two places: arm and riscv schema.
> 
> Are you going to have the same case?

We will likely never see any upstream DT for it but yes that's the same case.

Thanks,
Michal

Re: [PATCH v2 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc

[Krzysztof Kozlowski]

On 22/11/2023 10:13, Michal Simek wrote:
> All Xilinx boards can hosts also soft core CPUs like MicroBlaze or
> MicroBlaze V (RISC-V ISA) that's why move boar description from arm folder

With boar fixed:


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 2/2] dt-bindings: soc: Add new board description for MicroBlaze V

[Rob Herring]

On Wed, 22 Nov 2023 10:13:51 +0100, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor. Processor can
> be used with standard AMD/Xilinx IPs including interrupt controller and
> timer.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
> Changes in v2:
> - Put MicroBlaze V description to xilinx.yaml
> - Add qemu target platform as platform used for testing.
> 
>  Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/arm/xilinx.yaml:137:10: [warning] wrong indentation: expected 10 but found 9 (indentation)

dtschema/dtc warnings/errors:

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/e7af81b1ef3f6b7a07f4f0691f5140156477e87e.1700644418.git.michal.simek@amd.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.