From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Escande Subject: Re: [PATCH] arm64: msm8916: fix gic_irq_domain_translate warnings Date: Thu, 19 Apr 2018 16:49:21 +0200 Message-ID: <89454c94-dd62-80ca-6082-42cb24d43cf4@linaro.org> References: <20180418163415.21646-1-srinivas.kandagatla@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180418163415.21646-1-srinivas.kandagatla@linaro.org> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: srinivas.kandagatla@linaro.org, andy.gross@linaro.org, linux-arm-msm@vger.kernel.org Cc: david.brown@linaro.org, robh+dt@kernel.org, linux-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On 18/04/2018 18:34, srinivas.kandagatla@linaro.org wrote: > From: Srinivas Kandagatla > > Remove the usage of IRQ_TYPE_NONE to fix loud warnings from > patch (83a86fbb5b56b "irqchip/gic: Loudly complain about > the use of IRQ_TYPE_NONE"). > > Signed-off-by: Srinivas Kandagatla > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index cfbd72186762..5d66a575c7e1 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi Reviewed-by: Thierry Escande Also successfully tested on dragonboard 410c so: Tested-by: Thierry Escande > @@ -180,7 +180,7 @@ > > pmu { > compatible = "arm,cortex-a53-pmu"; > - interrupts = ; > + interrupts = ; > }; > > thermal-zones { > @@ -513,7 +513,7 @@ > blsp_i2c2: i2c@78b6000 { > compatible = "qcom,i2c-qup-v2.2.1"; > reg = <0x078b6000 0x500>; > - interrupts = ; > + interrupts = ; > clocks = <&gcc GCC_BLSP1_AHB_CLK>, > <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; > clock-names = "iface", "core"; > @@ -528,7 +528,7 @@ > blsp_i2c4: i2c@78b8000 { > compatible = "qcom,i2c-qup-v2.2.1"; > reg = <0x078b8000 0x500>; > - interrupts = ; > + interrupts = ; > clocks = <&gcc GCC_BLSP1_AHB_CLK>, > <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; > clock-names = "iface", "core"; > @@ -543,7 +543,7 @@ > blsp_i2c6: i2c@78ba000 { > compatible = "qcom,i2c-qup-v2.2.1"; > reg = <0x078ba000 0x500>; > - interrupts = ; > + interrupts = ; > clocks = <&gcc GCC_BLSP1_AHB_CLK>, > <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; > clock-names = "iface", "core"; > @@ -575,7 +575,7 @@ > "mi2s-bit-clk3"; > #sound-dai-cells = <1>; > > - interrupts = <0 160 0>; > + interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "lpass-irq-lpaif"; > reg = <0x07708000 0x10000>; > reg-names = "lpass-lpaif"; > @@ -595,7 +595,7 @@ > reg = <0x07824900 0x11c>, <0x07824000 0x800>; > reg-names = "hc_mem", "core_mem"; > > - interrupts = <0 123 0>, <0 138 0>; > + interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > clocks = <&gcc GCC_SDCC1_APPS_CLK>, > <&gcc GCC_SDCC1_AHB_CLK>, > @@ -612,7 +612,7 @@ > reg = <0x07864900 0x11c>, <0x07864000 0x800>; > reg-names = "hc_mem", "core_mem"; > > - interrupts = <0 125 0>, <0 221 0>; > + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > clocks = <&gcc GCC_SDCC2_APPS_CLK>, > <&gcc GCC_SDCC2_AHB_CLK>, > @@ -819,7 +819,7 @@ > iommu-ctx@2000 { > compatible = "qcom,msm-iommu-v1-ns"; > reg = <0x2000 0x1000>; > - interrupts = ; > + interrupts = ; > }; > }; > > @@ -864,7 +864,7 @@ > "bus_clk", > "vsync_clk"; > > - interrupts = <0 72 0>; > + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; > > interrupt-controller; > #interrupt-cells = <1>; >