From: <Conor.Dooley@microchip.com>
To: <zong.li@sifive.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<greentime.hu@sifive.com>, <ben.dooks@sifive.com>, <bp@alien8.de>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 6/6] soc: sifive: ccache: define the macro for the register shifts
Date: Thu, 8 Sep 2022 18:31:57 +0000 [thread overview]
Message-ID: <89e804ff-b451-c56a-a256-d3917e6c34b3@microchip.com> (raw)
In-Reply-To: <20220908144424.4232-7-zong.li@sifive.com>
On 08/09/2022 15:44, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Define the macro for the register shifts, it could make the code be
> more readable
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
Ahh my bad, I didn't realise you split it into another patch - sorry.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> drivers/soc/sifive/sifive_ccache.c | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index b3929c4d6d5b..0ddcc657c694 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -13,6 +13,7 @@
> #include <linux/of_irq.h>
> #include <linux/of_address.h>
> #include <linux/device.h>
> +#include <linux/bitfield.h>
> #include <asm/cacheinfo.h>
> #include <soc/sifive/sifive_ccache.h>
>
> @@ -33,6 +34,11 @@
> #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
>
> #define SIFIVE_CCACHE_CONFIG 0x00
> +#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)
> +#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)
> +#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
> +#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
> +
> #define SIFIVE_CCACHE_WAYENABLE 0x08
> #define SIFIVE_CCACHE_ECCINJECTERR 0x40
>
> @@ -87,11 +93,11 @@ static void ccache_config_read(void)
> u32 cfg;
>
> cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> -
> - pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> - (cfg & 0xff), (cfg >> 8) & 0xff,
> - BIT_ULL((cfg >> 16) & 0xff),
> - BIT_ULL((cfg >> 24) & 0xff));
> + pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",
> + FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),
> + FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),
> + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
> + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
>
> cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> pr_info("Index of the largest way enabled: %u\n", cfg);
> --
> 2.17.1
>
next prev parent reply other threads:[~2022-09-08 18:32 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-08 14:44 [PATCH v3 0/6] Use composable cache instead of L2 cache Zong Li
2022-09-08 14:44 ` [PATCH v3 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Zong Li
2022-09-08 14:44 ` [PATCH v3 2/6] soc: sifive: ccache: rename SiFive " Zong Li
2022-09-08 18:33 ` Conor.Dooley
2022-09-12 1:38 ` Zong Li
2022-09-08 14:44 ` [PATCH v3 3/6] soc: sifive: ccache: determine the cache level from dts Zong Li
2022-09-08 18:28 ` Conor.Dooley
2022-09-12 6:37 ` Zong Li
2022-09-08 14:44 ` [PATCH v3 4/6] soc: sifive: ccache: reduce printing on init Zong Li
2022-09-08 18:29 ` Conor.Dooley
2022-09-08 14:44 ` [PATCH v3 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li
2022-09-08 18:40 ` Conor.Dooley
2022-09-12 6:40 ` Zong Li
2022-09-08 14:44 ` [PATCH v3 6/6] soc: sifive: ccache: define the macro for the register shifts Zong Li
2022-09-08 18:31 ` Conor.Dooley [this message]
2022-09-08 14:51 ` [PATCH v3 0/6] Use composable cache instead of L2 cache Ben Dooks
2022-09-08 16:27 ` Zong Li
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