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[125.103.213.40]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3c83961sm177814725ad.38.2025.12.25.01.46.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Dec 2025 01:46:43 -0800 (PST) Content-Type: text/plain; charset=us-ascii Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3864.300.41.1.7\)) Subject: Re: [PATCH v4 6/9] riscv: dts: thead: add DPU and HDMI device tree nodes From: "Han Gao (Revy)" In-Reply-To: <20251224161205.1132149-7-zhengxingda@iscas.ac.cn> Date: Thu, 25 Dec 2025 17:46:26 +0800 Cc: "Han Gao (Revy)" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Content-Transfer-Encoding: quoted-printable Message-Id: <8A7BC047-96F9-4067-976F-282FA2AE8393@gmail.com> References: <20251224161205.1132149-1-zhengxingda@iscas.ac.cn> <20251224161205.1132149-7-zhengxingda@iscas.ac.cn> To: Icenowy Zheng X-Mailer: Apple Mail (2.3864.300.41.1.7) > On Dec 25, 2025, at 00:12, Icenowy Zheng = wrote: >=20 > From: Icenowy Zheng >=20 > T-Head TH1520 SoC contains a Verisilicon DC8200 display controller > (called DPU in manual) and a Synopsys DesignWare HDMI TX controller. >=20 > Add device tree nodes to them. >=20 > Signed-off-by: Icenowy Zheng > Signed-off-by: Icenowy Zheng > --- > No changes in v4. >=20 > Changes in v3: > - Adapting to the changed binding. >=20 > No changes in v2. >=20 > arch/riscv/boot/dts/thead/th1520.dtsi | 70 +++++++++++++++++++++++++++ > 1 file changed, 70 insertions(+) >=20 > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi = b/arch/riscv/boot/dts/thead/th1520.dtsi > index bd5d33840884e..5c0a7072f253a 100644 > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -585,6 +585,76 @@ clk_vo: clock-controller@ffef528050 { > #clock-cells =3D <1>; > }; >=20 > + hdmi: hdmi@ffef540000 { > + compatible =3D "thead,th1520-dw-hdmi"; > + reg =3D <0xff 0xef540000 0x0 0x40000>; > + reg-io-width =3D <4>; > + interrupts =3D <111 IRQ_TYPE_LEVEL_HIGH>; > + clocks =3D <&clk_vo CLK_HDMI_PCLK>, > + <&clk_vo CLK_HDMI_SFR>, > + <&clk_vo CLK_HDMI_CEC>, > + <&clk_vo CLK_HDMI_PIXCLK>; > + clock-names =3D "iahb", "isfr", "cec", "pix"; > + resets =3D <&rst TH1520_RESET_ID_HDMI>, > + <&rst TH1520_RESET_ID_HDMI_APB>; > + reset-names =3D "main", "apb"; > + status =3D "disabled"; > + > + ports { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + port@0 { > + reg =3D <0>; > + > + hdmi_in: endpoint { > + remote-endpoint =3D <&dpu_out_dp1>; > + }; > + }; > + > + hdmi_out_port: port@1 { > + reg =3D <1>; > + }; > + }; > + }; > + > + dpu: display@ffef600000 { > + compatible =3D "thead,th1520-dc8200", "verisilicon,dc"; > + reg =3D <0xff 0xef600000 0x0 0x100000>; > + interrupts =3D <93 IRQ_TYPE_LEVEL_HIGH>; > + clocks =3D <&clk_vo CLK_DPU_CCLK>, > + <&clk_vo CLK_DPU_ACLK>, > + <&clk_vo CLK_DPU_HCLK>, > + <&clk_vo CLK_DPU_PIXELCLK0>, > + <&clk_vo CLK_DPU_PIXELCLK1>; > + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; > + resets =3D <&rst TH1520_RESET_ID_DPU_CORE>, > + <&rst TH1520_RESET_ID_DPU_AXI>, > + <&rst TH1520_RESET_ID_DPU_AHB>; > + reset-names =3D "core", "axi", "ahb"; > + status =3D "disabled"; > + > + ports { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + dpu_port0: port@0 { > + reg =3D <0>; > + }; > + > + dpu_port1: port@1 { > + reg =3D <1>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + dpu_out_dp1: endpoint@1 { > + reg =3D <1>; > + remote-endpoint =3D <&hdmi_in>; > + }; > + }; > + }; > + }; > + > dmac0: dma-controller@ffefc00000 { > compatible =3D "snps,axi-dma-1.01a"; > reg =3D <0xff 0xefc00000 0x0 0x1000>; > --=20 > 2.52.0 >=20 Tested-by: Han Gao =