Re: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings

[Jacky Huang <ychuang570808@gmail.com>]

Dear Krzysztof,


Thanks for your advice.


On 2023/3/18 上午 12:03, Krzysztof Kozlowski wrote:
> On 17/03/2023 10:52, Jacky Huang wrote:
>> Dear Krzysztof,
>>
>> Thanks for your advice.
>>
>> On 2023/3/17 下午 05:13, Krzysztof Kozlowski wrote:
>>> On 17/03/2023 04:47, Jacky Huang wrote:
>>>>>> +
>>>>>> +  nuvoton,pll-mode:
>>>>>> +    description:
>>>>>> +      A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
>>>>>> +      EPLL, and VPLL in sequential. The operation mode value 0 is for
>>>>>> +      integer mode, 1 is for fractional mode, and 2 is for spread
>>>>>> +      spectrum mode.
>>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>>>>>> +    maxItems: 5
>>>>>> +    items:
>>>>>> +      minimum: 0
>>>>>> +      maximum: 2
>>>>> Why exactly this is suitable for DT?
>>>> I will use strings instead.
>>> I have doubts why PLL mode is a property of DT. Is this a board-specific
>>> property?
>> CA-PLL has mode 0 only.
>> DDRPLL, APLL, EPLL, and VPLL have the same PLL design that supports
>> integer mode, fractional mode, and spread spctrum mode. The PLL mode
>> is controlled by clock controller register. I think it's not board-specific.
> You described the feature but that does not answer why this is suitable
> in DT. If this is not board-specific, then it is implied by compatible,
> right? Or it does not have to be in DT at all.
>
>
> Best regards,
> Krzysztof


I got it now. Yes, at least DDR PLL and VPLL (video pixel clock) can be 
different on

different boards. You're right, it should be board specific. Thank you.

In the next version, I will move PLL property to board dts.


Best regards,

Jacky Huang