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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1903a180ca2sm1154475c88.6.2026.10.20.15.02.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Oct 2026 15:02:50 -0700 (PDT) Message-ID: <8ae43c5b-b99b-43ff-a56f-19f4d5dbe176@oss.qualcomm.com> Date: Tue, 20 Oct 2026 15:02:49 -0700 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/7] phy: qcom-mipi-csi2: Add sa8775p D-PHY support To: Bryan O'Donoghue , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, mani@kernel.org Cc: gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, loic.poulain@oss.qualcomm.com, vladimir.zapolskiy@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261016235502.2274268-1-anusha.nandi@oss.qualcomm.com> <20261016235502.2274268-5-anusha.nandi@oss.qualcomm.com> <392642ad-3bac-48bc-9199-8c3923c588c2@kernel.org> Content-Language: en-US From: Anusha Arun Nandi In-Reply-To: <392642ad-3bac-48bc-9199-8c3923c588c2@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDA4NyBTYWx0ZWRfX5PfJYgco3h+i RKoE59giUfUT59cWwl0TD6rCgUlFljGhtdSTia0OFihnztJ4HLzyuUPzbGrjk1YqdnK/xfDNphS Syqxnb1zLLnH+ctPJJwish+Skh3gpu4= X-Proofpoint-GUID: XSg599X5ybB_qczsRD2bvQmKUg5a7E2j X-Proofpoint-ORIG-GUID: XSg599X5ybB_qczsRD2bvQmKUg5a7E2j X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDA4NyBTYWx0ZWRfX5X0lyg2P2h3j LdQr6M2g1yBRGY1KauOUwdtzEwTCG8zuKMuH+S7yHqrEynr5gISlr/lRgkWEKadLrvWFUuq9xYI V+TCvVA+7sxLROsurtk2UA6PsgzjdXFHMdNHKo1CcuCgfcdrbiDs2fUSuxmRbEYyvEoJROH3f7T 3gu9+EeNw8oeYQAZzW+CwTPhlFQ+Mz2Inm2HGaXm/xoOVOCCt5io7LOx5fdiRnYS9WvH8JsZcFs mZy9N65M+E/4YU29tThkuGpdoujyELMQ378WjytwGKqCMrlqYgiF5jeAyeqTY5ICK9gZtXlJWNi 2klILd3fDhJMviKiMAyvNzCXcTisNtlCFvdC62pbjYbP8Cuv2Lvo7M7XFjaxwuNR7cGjhZIRtqE 6Qt2k4XJtB32pqgbrcNskMHGq5ZGSu4SragOels1cSI+z+F6yiCkw1RfiEtVHyVM2eSWn3H5Fug OUHisYU4Y8T7xMg697g== X-Authority-Analysis: v=2.4 cv=TcsDJhQh c=1 sm=1 tr=0 ts=6ad7e50d cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=VjktAE_kRdQNXcrMly4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_04,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200087 Hi Bryan, Thank you for the comments. Let me make the patches specific to the functionality and make it more granular in the next version of the patchset. I agree opp_clk is supposed to be optional, I will make a patch for it as well. Best Regards, Anusha On 10/19/2026 3:01 AM, Bryan O'Donoghue wrote: > On 17/10/2026 00:54, Anusha Arun Nandi wrote: >> The timer-clock lookup in phy_qcom_mipi_csi2_probe() and the OPP >> clkname passed to devm_pm_opp_set_clkname() were both hardcoded >> string literals sized to x1e80100 ("timer"/"core"). Add >> timer_clk_name/opp_clk_name to struct mipi_csi2phy_soc_cfg so each >> SoC can declare its own clock-name strings; x1e80100's soc_cfg now >> declares "timer"/"core" explicitly, with no behaviour change. >> SA8775P reuses the same "timer"/"core" names as x1e80100 for this >> pair of clocks. > > LoL I had that in the last design and review said "hard code it" happy > to agree with myself in the past, however this change should be > standalone and precede the Lemans work. > >> SA8775P's CSIPHY has a single power-domain, the Titan Top GDSC, >> matching the legacy in-tree CAMSS driver's sa8775p_resources.pd_name >> = "top" and the existing lemans.dtsi camss node. Like x1e80100's own >> "top" domain, it is not OPP-scaled, only kept enabled. >> >> Signed-off-by: Anusha Arun Nandi >> --- >>   .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c    | 112 ++++++++++++++++++ >>   .../phy/qualcomm/phy-qcom-mipi-csi2-core.c    |   5 +- >>   drivers/phy/qualcomm/phy-qcom-mipi-csi2.h     |   4 + >>   3 files changed, 119 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/ >> drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c >> index 966d79c98f9b..85e89235f7c9 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c >> +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c >> @@ -380,6 +380,118 @@ const struct mipi_csi2phy_soc_cfg >> mipi_csi2_dphy_4nm_x1e = { >>       .num_supplies = ARRAY_SIZE(x1e_supplies), >>       .clk_names = (const char **)x1e_clks, >>       .num_clk = ARRAY_SIZE(x1e_clks), >> +    .timer_clk_name = "timer", >> +    .opp_clk_name = "core", >>       .genpds = x1e_genpds, >>       .num_genpds = ARRAY_SIZE(x1e_genpds), >>   }; > > Yes but split it up - "remove hard coded timer and opp names" - actually > you want to make the OPP optional no ? In which case you'd expect to see > a patch to make OPPs optional - instead of folding that into a > functionality drop. > > Because say we want to revert or re-order the addition of Lemans in the > git log - we then have the problem of mixed functionality. > > Or say I want to cherry-pick a backport - I don't necessarily want to > include lots of SoC specific stuff that doesn't affect my part. > > => More granular patches. > > --- > bod