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Thu, 09 May 2024 15:52:10 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 449Fq927012208 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 9 May 2024 15:52:09 GMT Received: from [10.216.15.105] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 9 May 2024 08:52:00 -0700 Message-ID: <8b213eba-7ab6-ae9c-7683-937a9d6aaf08@quicinc.com> Date: Thu, 9 May 2024 21:21:55 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH v12 6/6] PCI: qcom: Add OPP support to scale performance Content-Language: en-US To: Manivannan Sadhasivam CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , , , , , , , , , , , , , References: <20240427-opp_support-v12-0-f6beb0a1f2fc@quicinc.com> <20240427-opp_support-v12-6-f6beb0a1f2fc@quicinc.com> <20240430052613.GD3301@thinkpad> From: Krishna Chaitanya Chundru In-Reply-To: <20240430052613.GD3301@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: e3kRQnlviW5VTpG8CYK6mD-swvONXwYd X-Proofpoint-ORIG-GUID: e3kRQnlviW5VTpG8CYK6mD-swvONXwYd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-09_08,2024-05-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 phishscore=0 adultscore=0 clxscore=1011 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405090107 On 4/30/2024 10:56 AM, Manivannan Sadhasivam wrote: > On Sat, Apr 27, 2024 at 07:22:39AM +0530, Krishna chaitanya chundru wrote: >> QCOM Resource Power Manager-hardened (RPMh) is a hardware block which >> maintains hardware state of a regulator by performing max aggregation of >> the requests made by all of the clients. >> >> PCIe controller can operate on different RPMh performance state of power >> domain based on the speed of the link. And this performance state varies >> from target to target, like some controllers support GEN3 in NOM (Nominal) >> voltage corner, while some other supports GEN3 in low SVS (static voltage >> scaling). >> >> The SoC can be more power efficient if we scale the performance state >> based on the aggregate PCIe link bandwidth. >> >> Add Operating Performance Points (OPP) support to vote for RPMh state based >> on the aggregate link bandwidth. >> >> OPP can handle ICC bw voting also, so move ICC bw voting through OPP >> framework if OPP entries are present. >> >> As we are moving ICC voting as part of OPP, don't initialize ICC if OPP >> is supported. >> >> Before PCIe link is initialized vote for highest OPP in the OPP table, >> so that we are voting for maximum voltage corner for the link to come up >> in maximum supported speed. >> >> Reviewed-by: Manivannan Sadhasivam >> Signed-off-by: Krishna chaitanya chundru >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 81 ++++++++++++++++++++++++++++------ >> 1 file changed, 67 insertions(+), 14 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 465d63b4be1c..40c875c518d8 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > [...] > >> @@ -1661,6 +1711,9 @@ static int qcom_pcie_suspend_noirq(struct device *dev) >> ret = icc_disable(pcie->icc_cpu); >> if (ret) >> dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); >> + >> + if (!pcie->icc_mem) >> + dev_pm_opp_set_opp(pcie->pci->dev, NULL); > > At the start of the suspend, there is a call to icc_set_bw() for PCIe-MEM path. > Don't you want to update it too? > > - Mani > if opp is supported we just need to call dev_pm_opp_set_opp() only once which will take care for both PCIe-MEM & CPU-PCIe path. so we are not adding explicitly there. - Krishna Chaitanya.