From: Krzysztof Kozlowski <krzk@kernel.org>
To: Nas Chung <nas.chung@chipsnmedia.com>,
mchehab@kernel.org, hverkuil@xs4all.nl, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de
Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org,
jackson.lee@chipsnmedia.com, lafley.kim@chipsnmedia.com,
marek.vasut@mailbox.org
Subject: Re: [PATCH v4 2/9] dt-bindings: media: nxp: Add Wave6 video codec device
Date: Wed, 22 Oct 2025 10:31:11 +0200 [thread overview]
Message-ID: <8b420cd2-9549-4033-b82f-a2bc145b7280@kernel.org> (raw)
In-Reply-To: <20251022074710.575-3-nas.chung@chipsnmedia.com>
On 22/10/2025 09:47, Nas Chung wrote:
> Add documentation for the Chips&Media Wave6 video codec on
> NXP i.MX SoCs.
>
> The Wave6 video codec functionality is split between a VPU
> control region and VPU core regions.
> The VPU control region is represented as the parent node and
> manages shared resources such as firmware memory. Each VPU
> core region is represented as a child node and provides the
> actual encoding and decoding capabilities.
>
> Both the control and core regions may be assigned IOMMU
> stream IDs for DMA isolation.
Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
>
> +
> + ranges: true
> +
> +patternProperties:
> + "^video-core@[0-9a-f]+$":
> + type: object
> + description:
> + A VPU core region within the Chips&Media Wave6 codec IP.
> + Each core provides encoding and decoding capabilities and operates
> + under the control of the VPU control region.
You explained more in previous email than in this description. Are these
independent? Can they be independently used?
But you also said there is one processing engine, so I do not understand
why these are separate. If you have one engine, there is no such thing
as separate cores.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-10-22 8:31 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 7:47 [PATCH v4 0/9] Add support for Wave6 video codec driver Nas Chung
2025-10-22 7:47 ` [PATCH v4 1/9] media: v4l2-common: Add YUV24 format info Nas Chung
2025-10-22 7:47 ` [PATCH v4 2/9] dt-bindings: media: nxp: Add Wave6 video codec device Nas Chung
2025-10-22 8:31 ` Krzysztof Kozlowski [this message]
2025-10-23 5:13 ` Nas Chung
2025-11-03 5:41 ` Nas Chung
2025-10-22 7:47 ` [PATCH v4 3/9] media: chips-media: wave6: Add Wave6 VPU interface Nas Chung
2025-12-10 19:53 ` Nicolas Dufresne
2025-10-22 7:47 ` [PATCH v4 4/9] media: chips-media: wave6: Add v4l2 m2m driver support Nas Chung
2025-10-22 7:47 ` [PATCH v4 5/9] media: chips-media: wave6: Add Wave6 core driver Nas Chung
2025-10-22 7:47 ` [PATCH v4 6/9] media: chips-media: wave6: Improve debugging capabilities Nas Chung
2025-10-22 7:47 ` [PATCH v4 7/9] media: chips-media: wave6: Add Wave6 thermal cooling device Nas Chung
2025-10-22 7:47 ` [PATCH v4 8/9] media: chips-media: wave6: Add Wave6 control driver Nas Chung
2025-10-22 23:01 ` kernel test robot
2025-10-23 0:03 ` kernel test robot
2025-10-22 7:47 ` [PATCH v4 9/9] arm64: dts: freescale: imx95: Add video codec node Nas Chung
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