From: Vignesh Raghavendra <vigneshr@ti.com>
To: Jayesh Choudhary <j-choudhary@ti.com>, <nm@ti.com>,
<devicetree@vger.kernel.org>
Cc: <kristo@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devarsht@ti.com>,
<u-kumar1@ti.com>
Subject: Re: [PATCH v2 3/7] arm64: dts: ti: k3-j721s2-main: add DSI & DSI PHY
Date: Thu, 26 Jun 2025 11:57:54 +0530 [thread overview]
Message-ID: <8c7f70eb-b64c-408d-816f-9adc997e42ec@ti.com> (raw)
In-Reply-To: <20250624082619.324851-4-j-choudhary@ti.com>
On 24/06/25 13:56, Jayesh Choudhary wrote:
> From: Rahul T R <r-ravikumar@ti.com>
>
> Add DT nodes for DPI to DSI Bridge and DSI Phy.
> The DSI bridge is Cadence DSI and the PHY is a
> Cadence DPHY with TI wrapper.
>
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> [j-choudhary@ti.com: disable dsi and dphy nodes, rename dphy node]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 37 ++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 83cf0adb2cb7..e17fffc36248 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -1795,6 +1795,43 @@ main_spi7: spi@2170000 {
> status = "disabled";
> };
>
> + dphy_tx0: phy@4480000 {
> + compatible = "ti,j721e-dphy";
> + reg = <0x0 0x04480000 0x0 0x1000>;
> + clocks = <&k3_clks 363 8>, <&k3_clks 363 14>;
> + clock-names = "psm", "pll_ref";
> + #phy-cells = <0>;
> + power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
> + assigned-clocks = <&k3_clks 363 14>;
> + assigned-clock-parents = <&k3_clks 363 15>;
> + assigned-clock-rates = <19200000>;
> + status = "disabled";
> + };
> +
> + dsi0: dsi@4800000 {
> + compatible = "ti,j721e-dsi";
> + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
> + clocks = <&k3_clks 154 4>, <&k3_clks 154 1>;
> + clock-names = "dsi_p_clk", "dsi_sys_clk";
> + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&dphy_tx0>;
> + phy-names = "dphy";
> + status = "disabled";
> +
> + dsi0_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + };
> + port@1 {
> + reg = <1>;
> + };
Messed up indentation
> + };
> + };
> +
> dss: dss@4a00000 {
> compatible = "ti,j721e-dss";
> reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
--
Regards
Vignesh
https://ti.com/opensource
next prev parent reply other threads:[~2025-06-26 6:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 8:26 [PATCH v2 0/7] Add DSI display support for TI's Jacinto platforms Jayesh Choudhary
2025-06-24 8:26 ` [PATCH v2 1/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: add DSI & DSI PHY Jayesh Choudhary
2025-06-26 6:26 ` Vignesh Raghavendra
2025-07-15 9:46 ` Jayesh Choudhary
2025-06-24 8:26 ` [PATCH v2 2/7] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable DisplayPort-1 Jayesh Choudhary
2025-06-24 8:26 ` [PATCH v2 3/7] arm64: dts: ti: k3-j721s2-main: add DSI & DSI PHY Jayesh Choudhary
2025-06-26 6:27 ` Vignesh Raghavendra [this message]
2025-06-24 8:26 ` [PATCH v2 4/7] arm64: dts: ti: k3-j721s2-common-proc-board: Add main_i2c4 instance Jayesh Choudhary
2025-06-26 10:26 ` Kumar, Udit
2025-06-24 8:26 ` [PATCH v2 5/7] arm64: dts: ti: k3-j721s2-som-p0: add DSI to eDP Jayesh Choudhary
2025-06-24 8:26 ` [PATCH v2 6/7] arm64: dts: ti: k3-j721s2-common-proc-board: Enable DisplayPort-1 Jayesh Choudhary
2025-06-26 10:34 ` Kumar, Udit
2025-07-16 5:42 ` Jayesh Choudhary
2025-06-24 8:26 ` [PATCH v2 7/7] arm64: dts: ti: k3-am68-sk: Enable DSI on DisplayPort-0 Jayesh Choudhary
2025-06-26 6:34 ` Vignesh Raghavendra
2025-07-15 9:48 ` Jayesh Choudhary
2025-06-26 6:15 ` [PATCH v2 0/7] Add DSI display support for TI's Jacinto platforms Vignesh Raghavendra
2025-07-15 9:43 ` Jayesh Choudhary
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