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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Content-Language: en-US To: Eric Lin Cc: conor@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, maz@kernel.org, chenhuacai@kernel.org, baolu.lu@linux.intel.com, will@kernel.org, kan.liang@linux.intel.com, nnac123@linux.ibm.com, pierre.gondois@arm.com, jgross@suse.com, chao.gao@intel.com, maobibo@loongson.cn, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dslin1010@gmail.com, Zong Li , Nick Hu , Greentime Hu References: <20230616063210.19063-1-eric.lin@sifive.com> <20230616063210.19063-4-eric.lin@sifive.com> <2437bda9-bbdb-ad80-7201-1e16e1388890@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 26/06/2023 05:26, Eric Lin wrote: > Hi Krzysztof, > > On Fri, Jun 16, 2023 at 6:45 PM Krzysztof Kozlowski > wrote: >> >> On 16/06/2023 08:32, Eric Lin wrote: >>> This add YAML DT binding documentation for SiFive Private L2 >>> cache controller >>> >>> Signed-off-by: Eric Lin >>> Reviewed-by: Zong Li >>> Reviewed-by: Nick Hu >>> --- >>> .../bindings/riscv/sifive,pL2Cache0.yaml | 81 +++++++++++++++++++ >>> 1 file changed, 81 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml >>> new file mode 100644 >>> index 000000000000..b5d8d4a39dde >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml >>> @@ -0,0 +1,81 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +# Copyright (C) 2023 SiFive, Inc. >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/riscv/sifive,pL2Cache0.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: SiFive Private L2 Cache Controller >>> + >>> +maintainers: >>> + - Greentime Hu >>> + - Eric Lin >>> + >>> +description: >>> + The SiFive Private L2 Cache Controller is per hart and communicates with both the upstream >>> + L1 caches and downstream L3 cache or memory, enabling a high-performance cache subsystem. >>> + All the properties in ePAPR/DeviceTree specification applies for this platform. >> >> Drop the last sentence. Why specification would not apply? >> > OK, I'll drop it in v2. > >>> + >>> +allOf: >>> + - $ref: /schemas/cache-controller.yaml# >>> + >>> +select: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - sifive,pL2Cache0 >>> + - sifive,pL2Cache >>> + >>> + required: >>> + - compatible >>> + >>> +properties: >>> + compatible: >>> + items: >> >> >> You have only one item, so no need for items... unless you just missed >> proper fallback. > > OK, I'll fix it in v2. > >> >>> + - enum: >>> + - sifive,pL2Cache0 >>> + - sifive,pL2Cache1 >> >> What is "0" and "1" here? What do these compatibles represent? Why they >> do not have any SoC related part? > > The pL2Cache1 has minor changes in hardware, but it can use the same > pl2 cache driver. Then why aren't they compatible? > May I ask, what do you mean about the SoC-related part? Thanks. This is part of a SoC, right? We expect SoC blocks to have compatible based on the SoC. Best regards, Krzysztof