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Wed, 10 Jul 2024 10:32:27 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46AAW7GV003609 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jul 2024 10:32:07 GMT Received: from [10.239.132.150] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 10 Jul 2024 03:32:01 -0700 Message-ID: <8caad754-0fa2-4158-86cd-b04101618638@quicinc.com> Date: Wed, 10 Jul 2024 18:31:58 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: qcom-ep: Add support for QCS9100 SoC To: Bjorn Helgaas , Tengfei Fan CC: Manivannan Sadhasivam , "Lorenzo Pieralisi" , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , , , , , References: <20240709162831.GA176079@bhelgaas> Content-Language: en-US From: "Aiqun Yu (Maria)" In-Reply-To: <20240709162831.GA176079@bhelgaas> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: HNumWH53y7d5tM552AkK3NtSI1ADf3VW X-Proofpoint-GUID: HNumWH53y7d5tM552AkK3NtSI1ADf3VW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-10_06,2024-07-10_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 adultscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407100072 On 7/10/2024 12:28 AM, Bjorn Helgaas wrote: > On Tue, Jul 09, 2024 at 10:53:43PM +0800, Tengfei Fan wrote: >> Add devicetree bindings support for QCS9100 SoC. It has DMA register >> space and dma interrupt to support HDMA. > > s/dma/DMA/ above for consistency. > > Add blank line here if this is a paragraph break. > >> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p >> platform use non-SCMI resource. In the future, the SA8775p platform will >> move to use SCMI resources and it will have new sa8775p-related device >> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to describe non-SCMI >> based PCIe. > > s/drived/derived/ > > This patch doesn't add anything related to SCMI, so this paragraph > seems like a distraction. The paragraph can be removed from the commit message in next patchsets. Let me know if others looks good to you or not. > > The first paragraph seems a bit of a distraction too, since the patch > doesn't say anything about DMA register space or interrupt. agree. Suggest to remove the first paragraph as well. > >> Signed-off-by: Tengfei Fan >> --- >> Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml >> index 46802f7d9482..8012663e7efc 100644 >> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml >> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml >> @@ -13,6 +13,7 @@ properties: >> compatible: >> oneOf: >> - enum: >> + - qcom,qcs9100-pcie-ep >> - qcom,sa8775p-pcie-ep >> - qcom,sdx55-pcie-ep >> - qcom,sm8450-pcie-ep >> @@ -203,6 +204,7 @@ allOf: >> compatible: >> contains: >> enum: >> + - qcom,qcs9100-pcie-ep >> - qcom,sa8775p-pcie-ep >> then: >> properties: >> >> -- >> 2.25.1 >> -- Thx and BRs, Aiqun(Maria) Yu