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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id d24-20020a056512369800b005091314185asm1952576lfs.285.2023.11.22.12.22.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Nov 2023 12:22:12 -0800 (PST) Message-ID: <8cece5d7-0fcb-4366-be72-6494842b7c41@linaro.org> Date: Wed, 22 Nov 2023 21:22:09 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC Content-Language: en-US To: Kathiravan Thirumoorthy , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> <20231121-ipq5332-nsscc-v2-8-a7ff61beab72@quicinc.com> From: Konrad Dybcio In-Reply-To: <20231121-ipq5332-nsscc-v2-8-a7ff61beab72@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Level: * On 11/21/23 15:30, Kathiravan Thirumoorthy wrote: > Describe the NSS clock controller node and it's relevant external > clocks. > > Signed-off-by: Kathiravan Thirumoorthy > --- > Changes in V2: > - Update the node names with proper suffix > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index 42e2e48b2bc3..5cbe72f03869 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -15,6 +15,18 @@ / { > #size-cells = <2>; > > clocks { > + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk { > + compatible = "fixed-clock"; > + clock-frequency = <200000000>; > + #clock-cells = <0>; > + }; > + > + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk { > + compatible = "fixed-clock"; > + clock-frequency = <300000000>; > + #clock-cells = <0>; > + }; > + > sleep_clk: sleep-clk { > compatible = "fixed-clock"; > #clock-cells = <0>; > @@ -473,6 +485,22 @@ frame@b128000 { > status = "disabled"; > }; > }; > + > + nsscc: clock-controller@39b00000{ > + compatible = "qcom,ipq5332-nsscc"; > + reg = <0x39b00000 0x80000>; > + clocks = <&cmn_pll_nss_200m_clk>, > + <&cmn_pll_nss_300m_clk>, > + <&gcc GPLL0_OUT_AUX>, > + <0>, > + <0>, > + <0>, > + <0>, > + <&xo_board>; > + #clock-cells = <0x1>; > + #reset-cells = <0x1>; 0x1 -> 1, it's a number and not a register Konrad