From mboxrd@z Thu Jan 1 00:00:00 1970 From: zhangfei Subject: Re: [PATCH v3 1/2] dt-bindings: Document the hi3660 reset bindings Date: Fri, 9 Dec 2016 10:00:53 +0800 Message-ID: <8d06d67a-1acd-9e46-24ef-f8de0713e099@linaro.org> References: <1480989092-31847-1-git-send-email-zhangfei.gao@linaro.org> <1480989092-31847-2-git-send-email-zhangfei.gao@linaro.org> <1481031753.3202.57.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <1481031753.3202.57.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Philipp Zabel Cc: Rob Herring , Arnd Bergmann , haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 2016年12月06日 21:42, Philipp Zabel wrote: > Am Dienstag, den 06.12.2016, 09:51 +0800 schrieb Zhangfei Gao: >> Add DT bindings documentation for hi3660 SoC reset controller. >> >> Signed-off-by: Zhangfei Gao >> --- >> .../bindings/reset/hisilicon,hi3660-reset.txt | 36 ++++++++++++++++++++++ >> 1 file changed, 36 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt >> >> diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt >> new file mode 100644 >> index 0000000..178e478 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt >> @@ -0,0 +1,36 @@ >> +Hisilicon System Reset Controller >> +====================================== >> + >> +Please also refer to reset.txt in this directory for common reset >> +controller binding usage. >> + >> +The reset controller registers are part of the system-ctl block on >> +hi3660 SoC. >> + >> +Required properties: >> +- compatible: should be >> + "hisilicon,hi3660-reset" >> +- #reset-cells: 2, see below >> +- hisi,rst-syscon: phandle of the reset's syscon. >> + >> +Example: >> + iomcu: iomcu@ffd7e000 { >> + compatible = "hisilicon,hi3660-iomcu", "syscon"; >> + reg = <0x0 0xffd7e000 0x0 0x1000>; >> + }; >> + >> + iomcu_rst: iomcu_rst_controller { >> + compatible = "hisilicon,hi3660-reset"; >> + hisi,rst-syscon = <&iomcu>; >> + #reset-cells = <2>; >> + }; >> + >> +Specifying reset lines connected to IP modules >> +============================================== >> +example: >> + >> + i2c0: i2c@..... { >> + ... >> + resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */ > Should this mention somewhere what register the offset is supposed to > point to? This is the address offset to the set register, with the > corresponding clear register being placed at offset + 4. How about this description. -- #reset-cells: 2, see below - hisi,rst-syscon: phandle of the reset's syscon. +- #reset-cells : Specifies the number of cells needed to encode a + reset source. The type shall be a and the value shall be 2. + + Cell #1 : offset of the reset assert control + register from the syscon register base + offset + 4: deassert control register + offset + 8: status control register + Cell #2 : bit position of the reset in the reset control register May paste in this thread for a clear view. Thanks -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html