From mboxrd@z Thu Jan 1 00:00:00 1970 From: Srinivas Kandagatla Subject: Re: [PATCH v4 2/3] PCI: qcom: add support to msm8996 PCIE controller Date: Tue, 15 Nov 2016 16:10:28 +0000 Message-ID: <8d0e9b19-5d6f-8be5-84be-d102817a6b21@linaro.org> References: <1479122155-13393-1-git-send-email-srinivas.kandagatla@linaro.org> <1479122155-13393-3-git-send-email-srinivas.kandagatla@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Stanimir Varbanov , linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 15/11/16 15:08, Stanimir Varbanov wrote: >>> I don't like MSM8996_ prefix. Could you invent a macro which depending >>> >> on controller selects proper offset? >> > >> > maybe some like this ?? >> > >> > #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 > No, I wanted to preserve the name of the register offset. By that way in > the next pcie controller version we do not need to have > PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V3. > > I was thinking for something like > > PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT(ver) \ > ((ver) == VERSION_1 ? 0x178 : 0x1A8) > > But you will need to extend qcom_pcie_ops with new member to store the > version. > > It's up to you ... or we can fix it when new version of the controller > appear. TBH, I don't want to add this just for this one case, looks bit over do. So I skipped to using V2 Suffix. We can fix later if required. --srini -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html