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Tue, 26 May 2026 00:38:11 -0700 (PDT) X-Received: by 2002:a05:6a21:394c:b0:3b2:86c9:baa5 with SMTP id adf61e73a8af0-3b328f3adb3mr18196142637.38.1779781091281; Tue, 26 May 2026 00:38:11 -0700 (PDT) Received: from [10.151.36.45] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c85202b3867sm9294952a12.11.2026.05.26.00.38.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 May 2026 00:38:10 -0700 (PDT) Message-ID: <8d9f78d2-d414-4ffb-bdf2-e2e7bda73aaf@oss.qualcomm.com> Date: Tue, 26 May 2026 13:08:05 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: soc: qcom: Document CDSP Power Management To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260520-cdsp-power-v1-0-85eb9501a1cd@oss.qualcomm.com> <20260520-cdsp-power-v1-1-85eb9501a1cd@oss.qualcomm.com> Content-Language: en-US From: Vignesh Viswanathan In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=IrYutr/g c=1 sm=1 tr=0 ts=6a154de4 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=CbSWp4jS9IVN9doBrZEA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: 6Ey19n4zWf9857f_xjQ8YCZtr1Mgr8bi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDA2NCBTYWx0ZWRfX45josndU8ZJL 3o2I/qy6O7ZPc2jJpegqEVBbsBr8XnQRxWUS0mflGauJSO+m+cxj5fXaWF4tp8+kEgMQx9QoNzU y+YbAmtqQ9coopFQKzL3bXm/pH1kvzTiUOgBEJjvzV6jBY27spgPSvDsjSCCi8idt7ILdFP1Qcv 1mHliGdbL19JgMqwAw65HNKejQoEnp2pQ0o0ihddKkfEDwQ9Xx+QyLvx9oejE/NlMCYhm/6jUbb tV4nWFmTsnTdb7LCgx5QudK6z8jWcXSuG8YtGXU4RTIx8NG3XRWCkkMyw166my1JJnT66D3onTY +xiZRrw7+ITwRWK3zefSxDg2rrXTHvshJkewkD2jhMt025xj3YVl3Kas/kE4H7udpDqh1v/EtCf TlCY/3M+VJkGSgDY2DK75xzQYS60FKc1M5YWd2UFIfDn+/8tx9zEzLuIdZfzBM9I1mgng0BpUDZ isRS0/nWzzcIGzemtDQ== X-Proofpoint-GUID: 6Ey19n4zWf9857f_xjQ8YCZtr1Mgr8bi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-26_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 phishscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605260064 On 5/20/2026 3:29 PM, Konrad Dybcio wrote: > On 5/19/26 9:05 PM, Vignesh Viswanathan wrote: >> Add documentation for the CDSP Power Management driver, which handles >> Dynamic Clock and Voltage Scaling (DCVS) requests via SMEM, manages Low >> Power Mode (LPM) transitions via MPM handshake, and provides virtual >> regulators for the remoteproc driver to control CDSP power rails. >> >> Signed-off-by: Vignesh Viswanathan >> --- > > [...] > >> +maintainers: >> + - Vignesh Viswanathan >> + >> +description: >> + The CDSP Power Management driver provides power management services for the >> + Qualcomm Compute DSP (CDSP) subsystem. It handles Dynamic Clock and Voltage >> + Scaling (DCVS) requests via SMEM, manages Low Power Mode (LPM) transitions >> + via MPM handshake, and provides virtual regulators that are consumed by the >> + CDSP remoteproc driver. >> + >> +properties: >> + compatible: >> + const: qcom,cdsp-power > > This really needs to be SoC-specific Ack, will make it specific to ipq9650. > >> + >> + reg: >> + items: >> + - description: MPM (Modem Power Manager) register region >> + - description: RSCC (RSC Configuration) register region > > I was under the impression that these two belong to separate > universes.. MPM registers are used to control the power mode for the CDSP. RSCC region has RSCC_BR_EVENT register from where the APSS reads which mode the CDSP wants to enter and executes the corresponding sequence in the MPM. > >> + vdd-cx-supply: >> + description: >> + Phandle to the CX voltage regulator. This is the actual hardware regulator >> + (e.g., from MP8899 PMIC) that supplies power to the CDSP CX rail. > > I believe the second sentence is wholly redundant Will drop this. > > [...] > >> + #include >> + #include >> + #include >> + >> + soc { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cdsp_power: cdsp-power@4ae000 { >> + compatible = "qcom,cdsp-power"; >> + reg = <0x0 0x004ae000 0x0 0x1000>, > > MPM is a top-level peripheral, but this is a slice dedicated to the > CDSP so maybe it'd pass, but.. > >> + <0x0 0x26018018 0x0 0x4>; > > This is a single random register within the CDSP's register space, so > we should definitely be able to describe this better.. Will document this more clearly in the next version. Thanks, Vignesh > > Konrad